L6256 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6256' PDF : 28 Pages View PDF
L6256
tection of the 12V Combo vs. a Dolphin chip
(3) the DAC write bit toggles every time a byte is written to the DAC. This provides confirmation that the write actually took place.
(4) Detects spurious or missing SCLK edge count between CSELB edges.
(5) flips state whenever either ACR or VCR is written to successfully. This bit can be used together with the TX_ERR bit to see whether data
was changed in the Dolphin.
(6) If the back EMF chop blanking comparator goes high during the PWM On_Del period, this bit is set to a one. See the back EMF section.
(7) bit is reset every time the register is accessed by the processor.
(8) current limit bit works in run mode as well as in start mode. If current limit is ever detected in run mode, the chip should be immediately
tristated.
(9) A1 in this bit indicates the correct (forward) phasing has been detected by the back EMF circuitry. Specifically, at the negative edge of
SP_CLK the back EMF comparator must be in the expected state, or else the bit is cleared. Updated on every negative SP_CLK edge.
SPINDLE CIRCUITRY SPECIFICATIONS
Spindle Circuitry Specifications
Symbol
Tbrake
SR
Parameter
Braking Time
Start Mode Current Limit (bipolar)
Start Mode Current Limit
Tolerance
Slew Rate
Vpwr current spiking
Test Conditions
Vemf = 7V
Rref = 62.5K 1%
Startup Ipeak
At speed (3)
At run speed
Slew Rate range adjustment
Run Mode Current Limit
Spindle Output Current Leakage
(6)
Snubber caps
Tristate
Min.
8
12
0.5:1
0.7
-100
Typ.
1.6
15
1.0
Max.
±7%
25%
2:1
1.6
+100
Unit
s (1)
A
of programmed
current (2)
V/µs
above spindle
run current
(4)
A
µA
0
0.01
µF 20%
(1) braking on the spindle motor must remain active for the full braking time. This parameter is guaranteed by a leakage specification. Full
power brake is 3 seconds maximum.
(2) excluding Vcc tolerances.
(3) Slew rate at startup is limited by the parasitic diode revrse recovery timeso that the peak current spikes in the power supply are no larger
than 25% above the motor run current.
(4) Slew circuitry must internally be able to drive stated snubber loads and be adjusted from 0.5 to 2 times the nominal value. This implies
that Rslew is able to be adjusted from 51K to 200K without causing circuit problems within the chip.
(5) Run mode current limit is strictly a protection mechanism to protect against spurious SP_CLKs or improperly programmed timing. Max
limit is a manifacturer limit determined by safe operating area considerations for the spindle FETs. The minimum limit determines the
maximum chip loading during run time. Since this is strictly an internal limit, tolerances on this value are very wide.
(6) Spindle Output Leakage must not interfere with back EMF sensing at any time.
Feedforward Circuitry Specifications
Symbol
toff min(1)
Parameter
Minimum off time
PWM to DC Conversion
Chop Frequency
PSRR, Spindle
Test Conditions
(2)
(3)
(4)
Min.
100
32
Typ.
20/SR
110
22
-
Max.
-
-
Unit
µs
% of full scale
KHz
dB
(1)The purpose of toff min is to guarantee a full rise and fall time of the spindle chopper output circuitry at the minimum supply voltage. The
timing circuit which determines toff min internally tracks the slew rate circuitry to keep this relationship true, while keeping toff min as
small as possible.
NOTE: dynamic current limit considerations will usually limit the off time even further.
(2) For the PWM to DC conversion, the following standard conditions apply:
Rpwm = 33K 5%
Input impedance of processor driver, 100 ohms
Assume driver is at 100% duty cycle
Rpwmdc = 100K 5%
Cdc = .0033 µF 5%
At these values, the output produces toff min at Vpwr = 10 volts so that full scale is reachable.
(3) With Rslew = 100K 1%, Cffc = 470 pF 5%, and including chip input capacitance, the output must not go below 20 Khz over the range of
toff min values.
(4) PSRR is defined as the ratio of average output voltage to the motor over the Vpwr change: -20log10(dVout/dVpwr)
It is tested by injecting a 0.6V peak square wave on Vpwr and Vdd from 1 Hz to 10 kHz. The specification applies over the entire Vpwr
range.
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