L6256 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6256' PDF : 28 Pages View PDF
L6256
Auxiliary Control Register
Bit Function
Start (1)
VCM enable (2)
Spindle enable (3)
Thermal Limit
Test Enable (7)
Software POR
Spare
Register Brake
Mnemonic
START
VC_EN
SP_EN
OVTEMP
T_EN
SPOR
RBRAKE
Address: 0111
Init State
xxx
0
0
0
0
off
disabled (4)
R/W Bit # Read 1 indicates:
W
0
N/A
W
1
enabled (5)
W
2
enabled (5)
R
3
Th Limit
W
4
enabled (5)
W
5
always 0 (5)
R/W
7
Braking * (6)
NOTES:
(1) Start disables slew rate control. It also changes the back EMF detection circuitry from 3 phase to single phase.
(2) shuts down active circuitry and drives to the ground state when 0. A transition on this bit is required to reactivate the VCM. see state dia-
gram.
(3) shuts down active circuitry and tristates when 0. A transition on this bit is required to reactivate the spindle circuitry. see state diagram.
(4) Writing to brake will cause a register park, then a brake sequence (an internal POR), without causing an external POR\. Thus, the rest of
the system including the processor will not be reset.
(5) Optional bits.
(6) The register brake function has been redesigned to allow use of a momentary, current limited brake during start mode only. Asserting this
bit overrides the CCTR or CPR register contents without disturbing them, and causes a brake on the spindle outputs.
Resetting the bit restores the previous state ( the outputs were in before the bit was asserted). DO NOT attempt to change the CCTR or
CPR, or send a SP_CLK while this bit is asserted.
(7) Test Enable is used to enable manufacturer specific test circuitry within the chip. This bit should be initialized with a 0 value and left at 0
at all times. Do not attempt to use this bit for any reason unless you have complete manufacturer specific information.
Test Register
Address: 1000
Bit Function
Init State
R/W
Read 1 indicates:
Bits: TBD
up to 16 read, 8 write
NOTE: The test register requires 2 level access. That is, the test enable bit in the Aux Control Register must be written to with a 1 or the test
register is locked out.
Status Register (read only)
Status Bit
Dead Bit (unusable for timing reasons)
UV detect
Overtemperature Warning
Overtemperature Shutdown
Version Number (2 bits)
Vendor Number
Spindle Current Limit
Dead Bit (unusable for timing reasons)
EMF XOR Output
EMF A Comparator Output
DAC write
Transmission Error
Aux_Write
Phase Detect
Spindle Forward
Mnemonic
-
UV_DET *
TWARN
OVTEMP
VERS *
VENDOR
SILIM
EMFX
EMFA
XOR
TX_ERR *
AUX_WR
PH_DET
SP_FWD *
Address: 0100
High Indicates
n/a
Undervoltage Occuring
Exceeded Warning Temp
Exceeded Shutdown Temp (1)
(2)
(2)
Current Has Exceeded
threshold (7) (8)
n/a
Changes state on XOR of
Comparator A, B, C
Positive High
Write (3)
CSELB occurs during active
transmission (4) (7)
Toggles (5)
Correct PWM phasing (6)
Reports correct spindle
rotation direction
Address
Bit 0
Bit 1
Bit 2
Bit 3
4 = Bit 0
5 =Bit 1
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
NOTE: the status register is readable during a POR\ for in circuit testability.
(1) Overtemperature Shutdown or Warning do not cause POR\. This arrangement allows graceful recovery from overtemperature conditions.
(2) Vendor bit = 0 for Unitrode, 1 for ST. Version number, Bits 0,1 allow 4 chip versions. For the Dolphin: Bit 0 = 1, Bit 1 = 0. This allows de-
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