LH28F008SC-V/SCH-V
6.2.1 CAPACITANCE (NOTE 1)
SYMBOL
PARAMETER
CIN
Input Capacitance
COUT
Output Capacitance
NOTE :
1. Sampled, not 100% tested.
TA = +25˚C, f = 1 MHz
TYP.
MAX.
6
8
8
12
UNIT
pF
pF
CONDITION
VIN = 0.0 V
VOUT = 0.0 V
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
3.0
INPUT
1.5
TEST POINTS
1.5 OUTPUT
0.0
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output
timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 9 Transient Input/Output Reference Waveform for VCC = 5.0±0.25 V
(High Speed Testing Configuration)
2.4
INPUT
0.45
2.0
TEST POINTS
0.8
2.0
OUTPUT
0.8
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing
begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to
90%) < 10 ns.
Fig. 10 Transient Input/Output Reference Waveform for VCC = 5.0±0.5 V
(Standard Testing Configuration)
1.3 V
1N914
DEVICE
UNDER
TEST
CL Includes Jig
Capacitance
RL = 3.3 kΩ
OUT
CL
Test Configuration Capacitance Loading Value
TEST CONFIGURATION
CL (pF)
VCC = 5.0±0.25 V (NOTE 1)
30
VCC = 5.0±0.5 V
100
NOTE :
1. Applied to high-speed products, LH28F008SC-V85 and
LH28F008SCH-V85.
Fig. 11 Transient Equivalent Testing
Load Circuit
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