LH28F008SCB-V12 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F008SCB-V12' PDF : 40 Pages View PDF
LH28F008SC-V/SCH-V
6.2.3 DC CHARACTERISTICS (contd.)
SYMBOL
PARAMETER
VIL Input Low Voltage
NOTE
7
VCC = 5.0±0.5 V
MIN.
MAX.
– 0.5
0.8
UNIT
V
TEST
CONDITIONS
VIH Input High Voltage
7
2.0
VCC
V
+0.5
VOL Output Low Voltage
Output High Voltage
VOH1 (TTL)
3, 7
3, 7
2.4
0.45
VCC = VCC Min.
V
IOL = 5.8 mA
VCC = VCC Min.
V
IOH = –2.5 mA
Output High Voltage
VOH2
(CMOS)
0.85
VCC
3, 7
VCC
– 0.4
VCC = VCC Min.
V
IOH = –2.5 mA
VCC = VCC Min.
V
IOH = –100 µA
VPP Lockout Voltage during
VPPLK
4, 7
Normal Operations
1.5
V
VPP Voltage during Byte Write,
VPPH1
Block Erase or Lock-Bit Operations
4.5
5.5
V
VPP Voltage during Byte Write,
VPPH2
Block Erase or Lock-Bit Operations
11.4
12.6 V
VLKO VCC Lockout Voltage
VHH RP# Unlock Voltage
2.0
8, 9 11.4
V
Set master lock-bit
12.6 V Override master and
block lock-bit
NOTES :
1. All currents are in RMS unless otherwise noted. Typical
values at nominal VCC voltage and TA = +25˚C. These
currents are valid for all product versions (packages and
speeds).
2. ICCWS and ICCES are specified with the device de-
selected. If reading or byte writing in erase suspend
mode, the device’s current draw is the sum of ICCWS or
ICCES and ICCR or ICCW, respectively.
3. Includes RY/BY#.
4. Block erases, byte writes, and lock-bit configurations are
inhibited when VPP ≤ VPPLK, and not guaranteed in the
range between VPPLK (max.) and VPPH1 (min.), between
VPPH1 (max.) and VPPH2 (min.), and above VPPH2 (max.).
5. Automatic Power Saving (APS) reduces typical ICCR to
1 mA at 5 V VCC in static operation.
6. CMOS inputs are either VCC±0.2 V or GND±0.2 V. TTL
inputs are either VIL or VIH.
7. Sampled, not 100% tested.
8. Master lock-bit set operations are inhibited when RP# =
VIH. Block lock-bit configuration operations are inhibited
when the master lock-bit is set and RP# = VIH. Block
erases and byte writes are inhibited when the
corresponding block lock-bit is set and RP# = VIH. Block
erase, byte write, and lock-bit configuration operations
are not guaranteed with VIH < RP# < VHH and should not
be attempted.
9. RP# connection to a VHH supply is allowed for a
maximum cumulative period of 80 hours.
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