LH28F016SCH-L View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F016SCH-L' PDF : 44 Pages View PDF
LH28F016SC-L/SCH-L
Start
Write 60H
Write D0H
Read
Status Register
SR.7 = 0
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
BUS
OPERATION
Write
Write
COMMAND
Clear Block
Lock-Bits
Setup
Clear Block
Lock-Bits
Confirm
COMMENTS
Data = 60H
Addr = X
Data = D0H
Addr = X
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write FFH after the last clear block lock-bits operation to place
device in read array mode.
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1
SR.3 =
0
VPP Range Error
1
SR.1 =
0
Device Protect Error
1
SR.4, 5 =
0
Command Sequence
Error
1
SR.5 =
0
Clear Block Lock-Bits
Error
Clear Block Lock-Bits
Successful
BUS
OPERATION COMMAND
COMMENTS
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
RP# = VIH, Master Lock-Bit is Set
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Clear Block Lock-Bits Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command.
If error is detected, clear the status register before attempting
retry or other error recovery.
Fig. 8 Clear Block Lock-Bits Flowchart
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