LH28F016SCH-L View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F016SCH-L' PDF : 44 Pages View PDF
LH28F016SC-L/SCH-L
6.2.3 DC CHARACTERISTICS (contd.)
SYMBOL
PARAMETER
VIL Input Low Voltage
NOTE VCC = 2.7 to 3.6 V VCC = 3.3±0.3 V VCC = 5.0±0.5 V UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
7 –0.5 0.8 –0.5 0.8 –0.5 0.8 V
TEST
CONDITIONS
VIH Input High Voltage
7
2.0
VCC
+0.5
2.0
VCC
+0.5
2.0
VCC
+0.5
V
VOL Output Low Voltage
3, 7
0.4
VCC = VCC Min.
0.4
0.45 V IOL = 5.8 mA (5 V)
IOL = 2.0 mA (3.3 V, 2.7 V)
Output High Voltage
VOH1 (TTL)
Output High Voltage
VOH2 (CMOS)
3, 7 2.4
0.85
VCC
3, 7 VCC
– 0.4
2.4
0.85
VCC
VCC
– 0.4
2.4
0.85
VCC
VCC
– 0.4
VCC = VCC Min.
V IOH = –2.5 mA (5 V)
IOH = –2.0 mA (3.3 V, 2.7 V)
VCC = VCC Min.
V IOH = –2.5 mA
VCC = VCC Min.
V IOH = –100 µA
VPPLK
VPP Lockout Voltage during
Normal Operations
4, 7
1.5
1.5
1.5 V
VPP Voltage during
VPPH1 Byte Write, Block Erase
— — 3.0 3.6 — — V
or Lock-Bit Operations
VPP Voltage during
VPPH2 Byte Write, Block Erase
— — 4.5 5.5 4.5 5.5 V
or Lock-Bit Operations
VPP Voltage during
VPPH3 Byte Write, Block Erase
— — 11.4 12.6 11.4 12.6 V
or Lock-Bit Operations
VLKO VCC Lockout Voltage
2.0
2.0
2.0
V
Set master lock-bit
VHH RP# Unlock Voltage
8, 9 — — 11.4 12.6 11.4 12.6 V Override master and
block lock-bit
NOTES :
1. All currents are in RMS unless otherwise noted. Typical
6. CMOS inputs are either VCC±0.2 V or GND±0.2 V. TTL
values at nominal VCC voltage and TA = +25˚C. These
inputs are either VIL or VIH.
currents are valid for all product versions (packages and
7. Sampled, not 100% tested.
speeds).
8. Master lock-bit set operations are inhibited when RP# =
2. ICCWS and ICCES are specified with the device de-
VIH. Block lock-bit configuration operations are inhibited
selected. If reading or byte writing in erase suspend
when the master lock-bit is set and RP# = VIH. Block
mode, the device’s current draw is the sum of ICCWS or
erases and byte writes are inhibited when the
ICCES and ICCR or ICCW, respectively.
corresponding block lock-bit is set and RP# = VIH. Block
3. Includes RY/BY#.
erase, byte write, and lock-bit configuration operations
4. Block erases, byte writes, and lock-bit configurations are
are not guaranteed with VCC < 3.0 V or VIH < RP# <
inhibited when VPP ≤ VPPLK, and not guaranteed in the
VHH and should not be attempted.
range between VPPLK (max.) and VPPH1 (min.), between
9. RP# connection to a VHH supply is allowed for a
VPPH1 (max.) and VPPH2 (min.), between VPPH2 (max.)
maximum cumulative period of 80 hours.
and VPPH3 (min.), and above VPPH3 (max.).
5. Automatic Power Saving (APS) reduces typical ICCR to
1 mA at 5 V VCC and 3 mA at 2.7 V and 3.3 V VCC in
static operation.
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