LH28F016SCH-L View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F016SCH-L' PDF : 44 Pages View PDF
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections.
Three-line control provides for :
a. Lowest possible memory power consumption.
b. Complete assurance that data bus contention
will not occur.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2 RY/BY# and Block Erase, Byte Write,
and Lock-Bit Configuration Polling
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase, byte
write and lock-bit configuration completion. It
transitions low after block erase, byte write, or lock-
bit configuration commands and returns to VOH
when the WSM has finished executing the internal
algorithm.
RY/BY# can be connected to an interrupt input of
the system CPU or controller. It is active at all
times. RY/BY# is also VOH when the device is in
block erase suspend (with byte write inactive), byte
write suspend or deep power-down modes.
5.3 Power Supply Decoupling
Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current
LH28F016SC-L/SCH-L
issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device
should have a 0.1 µF ceramic capacitor connected
between its VCC and GND and between its VPP
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 µF electrolytic capacitor should be placed at
the array’s power supply connection between VCC
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
5.4 VPP Trace on Printed Circuit Boards
Updating flash memories that reside in the target
system requires that the printed circuit board
designers pay attention to the VPP power supply
trace. The VPP pin supplies the memory cell current
for byte writing and block erasing. Use similar trace
widths and layout considerations given to the VCC
power bus. Adequate VPP supply traces and
decoupling will decrease VPP voltage spikes and
overshoots.
5.5 VCC, VPP, RP# Transitions
Block erase, byte write and lock-bit configuration
are not guaranteed if VPP falls outside of a valid
VPPH1/2/3 range, VCC falls outside of a valid VCC2/3/4
range, or RP# ≠ VIH or VHH. If VPP error is
detected, status register bit SR.3 is set to "1" along
with SR.4 or SR.5, depending on the attempted
operation. If RP# transitions to VIL during block
erase, byte write, or lock-bit configuration, RY/BY#
will remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. The aborted operation
may leave data partially altered. Therefore, the
command sequence must be repeated after normal
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