LH28F040SUTD-Z4 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F040SUTD-Z4' PDF : 32 Pages View PDF
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
START
(NOTE)
WRITE A7H
WRITE D0H
READ COMPATIBLE
STATUS REGISTER
SUSPEND
NO ERASE LOOP
CSR.7 = 0
SUSPEND YES
ERASE
1
CSR FULL STATUS
CHECK IF DESIRED
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
BUS
OPERATION
COMMAND
COMMENTS
Write
Erase All
Unlocked
Blocks
D = A7H
A=X
Write
Read
Standby
Confirm
D = D0H
A=X
Q = CSRD
Toggle BE0, BE1 or OE
to update CSRD.
A=X
Check CSR.7
1 = WSM Ready
0 = WSM Busy
CSR Full Status Check can be done after Erase All Unlocked
Block, or after a sequence of Erasures.
Write FFH after the last operation to reset
device to read array mode.
See Command Bus Cycle notes for description of codes.
NOTE:
Where power off or reset during erase operation,
1. Clear CSR.3/4/5 and issue Reset WP command,
2. Retry Erase All Unlocked Block Erase command to
erase all blocks, or issue Single Block Erase to
erase all of the unlocked blocks in sequence.
3. Set WP command is issued, if necessary.
READ CSRD
(see above)
CSR.4, 5 = 0
1
ERASE
SUCCESSFUL
CSR.3 = 1
0
CLEAR CSRD
RETRY/ERROR
RECOVERY
(NOTE)
VPP LOW
DETECT
BUS
OPERATION
COMMAND
COMMENTS
Standby
Check CSR.4, 5
1 = Erase Error
0 = Erase Successful
Both 1 = Command
Sequence Error
Standby
Check CSR.3
1 = VPP Low Detect
0 = VPP OK
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
NOTE:
If CSR.3 (VPPS) is set to '1', after clearing CSR.3/4/5,
1. Issue Reset WP command,
2. Retry Erase All Unlocked Block Erase command to erase
all blocks, or issue Single Block Erase to erase all of the
unlocked blocks in sequence.
3. Set WP command is issued, if necessary.
If CSR.3 (VPPS) is set to '0', after clearing CSR.3/4/5,
1. Retry Erase All Unlocked Block Erase command.
Figure 10. Bank Erase All Unlocked Blocks with Compatible Status Registers
28F040SUZ4-10
16
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