LH28F400SU-LC
4M (512K × 8, 256K × 16) Flash Memory
DEEP
POWER-DOWN
ADDRESSES (A) VIH
(NOTE 1)
VIL
ADDRESSES (A) VIH
(NOTE 2)
VIL
WRITE
DATA-WRITE
OR ERASE
SETUP COMMAND
WRITE VALID
ADDRESS AND DATA
(DATA-WRITE) OR
ERASE CONFIRM
COMMAND
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
AIN
tAVAV
tAVWH
tWHAX
tAVAV
AIN
tAVWH tWHAX
(NOTE 3)
READ
COMPATIBLE
STATUS
REGISTER DATA
CE (E) VIH
VIL
OE (G) VIH
VIL
WE (W) VIH
VIL
tWHEH
tELWL
tWHWL
tWLWH
tWHDX
tWHGL
tWHQV 1, 2
tGHWL
DATA (D/Q) VIH
VIL
HIGH-Z
tPHWL
tDVWH
DIN
DIN
tWHRL
RY/BY (R) VOH
VOL
DIN
DOUT
DIN
tRHPL
RP (P) VIH
VIL
VPPH
VPP (V) VPPL
tVPWH
(NOTE 4)
tQVVL
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. RP low transition is only to show tRHPL; not valid for above Read and Write cycles.
Figure 19. AC Waveforms for Command Write Operations
28F004SU-Z9-19
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