LH543621 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543621' PDF : 57 Pages View PDF
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
OPERATIONAL DESCRIPTION (cont’d)
MBF2), which is synchronized to the reading port’s clock.
These New-Mail-Alert Flags are status indicators only,
and cannot inhibit mailbox-register read or write operations.
Request Acknowledge Handshake
A synchronous request-acknowledge handshake fea-
ture is provided for each port, to perform boundary syn-
chronization between asynchronously-operated ports.
The use of this feature is optional. When it is used, the
Request input (REQA/B) is sampled at a rising clock edge.
With REQA/B HIGH, R/WA/B determines whether a FIFO
read operation or a FIFO write operation is being re-
quested. The Acknowledge output (ACKA/B) is updated
during the following clock cycle(s). ACKA/B meets the
setup and hold time requirements of the Enable input
(ENA or ENB). Therefore, ACKA/B may be tied back to the
enable input to directly gate FIFO accesses, at a slight
decrease in maximum operating frequency.
The assertion of ACKA/B signifies that REQA/B was
asserted. However, ACKA/B does not depend logically on
ENA/B; and thus the assertion of ACKA/B does not prove
that a FIFO write access or a FIFO read access actually
took place. While REQA/B and ENA/B are being held
HIGH, ACKA/B may be considered as a synchronous,
predictive boundary flag. That is, ACKA/B acts as a
synchronized predictorofthe Almost-Full Flag AF for write
operations, or as a synchronized predictor of the Almost-
Empty Flag AE for read operations.
Outside the ‘almost-full’ region and the ‘almost-empty’
region, ACKA/B remains continuously HIGH whenever
REQA/B is held continuously HIGH. Within the ‘almost-full’
region or the ‘almost-empty’ region, ACKA/B occurs only
on every third cycle, to prevent an overrun of the FIFO’s
actual full or empty boundaries and to ensure that the tFWL
(first write latency) and tFRL (first read latency) specifica-
tions are satisfied before ACKA/B is received.
The ‘almost-full region’ is defined as ‘thatregion, where
the Almost-Full Flag is being asserted’; and the ‘almost-
empty region’ as ‘that region, where the Almost-Empty
Flag is being asserted.’ Thus, the extent of these ‘almost’
regions depends on how the system has programmed the
offset values for the Almost-Full Flags and the Almost-
Empty Flags. If the system has not programmed them,
then these offset values remain at their default values,
eight in each case.
If a write attempt is unsuccessful because the corre-
sponding FIFO is full, or if a read attempt is unsuccessful
because the corresponding FIFO is empty, ACKA/B is not
asserted in response to REQA/B.
If the REQ/ACK handshake is not used, then the
REQA/B input may be used as a second enable input, at
a possible minor loss in maximum operating speed. In this
case, the ACKA/B output may be ignored.
WARNING: Whether or not the REQ/ACK handshake is
being used, the REQA/B input for a port must be asserted
for that port to function at all – for FIFO, mailbox, or data-
bypass operation.
Data Retransmit
Aretransmit operation resets the read-address pointerof
the corresponding FIFO (#1 or #2) back to the first FIFO
physical memory location, so that data may be reread. The
write pointer is not affected. The status flags are updated;
and a block of up to 512 or 1024 data words, which
previously had been written into and read from a FIFO, can
be retrieved. The block to be retransmitted is bounded by
the first FIFO memory location, and the FIFO memory
location addressed by the write pointer. FIFO #1 retransmit
is initiated by strobing the RT1 pin LOW. FIFO #2 retransmit
is initiated by strobing the RT2 pin LOW. Read and write
operations to a FIFO should be stopped while the corre-
sponding Retransmit signal is being asserted.
Parity Checking
The Parity Check Flags, PFA and PFB, are asserted
(LOW) whenever there is a parity error in the data word
present on the Port A data bus or the Port B data bus
respectively. The inputs to the parity-evaluation logic
come directly (via isolation transistors) from the data-bus
bonding pads, in each case. Thus, PFA and PFB provide
parity-error indications for whatever 36-bit words are
present at Port A and Port B respectively, regardless of
whether those words originated within the LH543611/21
or in the external system.
The four bytes of a 36-bit data word are grouped as
D0 – D8, D9 – D17, D18 – D26, and D27 – D35. The parity of
each nine-bit byte is individually checked, and the four
single-bit parity indications are logically ORed and inverted
to produce the Parity-Flag output.
If the Parity Policy bit (Control-Register bit 09) is HIGH,
then parity at Port B will be computed over the field
defined by the Word-Width Selection control inputs WS0
and WS1, and then may be for full-words, for half-words,
or for single bytes. Otherwise, parity will be computed
over full-words regardless of the setting of WS0 and WS1.
Parity checking is initialized for odd parity at reset, but
can be reprogrammed for even parity or for odd parity
during operation. Control-Register bit 00 (zero) selects
the parity mode, odd or even. (See Tables 3, 5, and 6, and
Figure 10.)
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