LH543621 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543621' PDF : 57 Pages View PDF
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
PORT B WORD-WIDTH SELECTION
LH543611/21
PORT
A
36-Bit Data Stream
18-Bit Data Stream
D35A
18
D18A
(2Bnitds H18a-lf3w5ord)
D17A
18
D0A
Bits 0-17
(1st Halfword)
D35B
18
D18B
D17B
18
D0B
PORT
B
1st Halfword, then 2nd Halfword
543611-17
Figure 9a. 18-to-36 Defunneling Through FIFO #2
36-Bit Data Stream
D35A
9
D27A
Bits 27-35
(4th Byte)
9-Bit Data Stream
D35B
9
D27B
PORT
A
D26A
9
D18A
D17A
9
D9A
Bits 18-26
(3rd Byte)
Bits 9-17
(2nd Byte)
D26B
9
D18B
D17B
9
D9B
PORT
B
D8A
9
D0A
Bits 0-8
(1st Byte)
D8B
9
D0B
1st Byte, then 2nd Byte, then 3rd Byte, then 4th Byte
543611-18
Figure 9b. 9-to-36 Defunneling Through FIFO #2
NOTES:
1. The heavy black borders on register segments indicate the only
data paths used. The other byte segments of Port B do not par-
ticipate in the data path during defunneling.
2. The defunneling process does not change the ordering of bits
within a byte. Halfwords (Figure 9a) or bytes (Figure 9b) are
transferred in parallel form from Port B to Port A.
3. The word-width setting may be changed during system operation;
however, two clock intervals should be allowed for these signals
to settle, before again attempting to send data. Also, incomplete
data words may occur, when the word width is changed from
shorter to longer at an inappropriate point in the data block pass-
ing through the FIFO.
17
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