LH543611/21
TIMING DIAGRAMS (cont’d)
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
CKB
tRWS
R/WB
ENB
REQB
RT1
tES tEH
tES tEH
tRQS tRQH
tRQS tRQH
t RSH
t RS
t RSH
t ES
tRQS
tRSS
t RSS
CKA
tRWS
R/WA
ENA
tES t EH
tRQS tRQH
t ES t EH
tRQS tRQH
t ES
tRQS
REQA
NOTES:
1. tRSS and tRSH need not be met unless a rising edge of CKA or CKB occurs while that clock is enabled.
2. tRSS is the time needed to deassert RT1 before returning to a normal FIFO cycle.
3. tRSH is the time needed before asserting RT1 after a normal FIFO cycle.
4. Read and write operations to FIFO #1 should be disabled while RT1 is being asserted.
Figure 30. FIFO #1 Retransmit
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