LH543621 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543621' PDF : 57 Pages View PDF
LH543611/21
TIMING DIAGRAMS (cont’d)
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
CKB
R/WB
ENB
REQB
D0B - D35B
tRWH tRWS
t RWH
tRWS
tEH
t ES
tEH
t ES
tRQH tRQS
tRQH tRQS
tDH
tDS
tDH
tDS
t FWL
t FF
FF2
CKA
t FF
tRWH tRWS
tRWH tRWS
R/WA
tEH
t ES
tEH
t ES
ENA
tRQH tRQS
tRQH tRQS
REQA
tA
tA
t OH
t OH
D0A - D35A
PREVIOUS DATA
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. OEB is held HIGH.
3. OEA is held LOW.
4. tFWL (First Write Latency) - The first write following a full condition
may begin no earlier than tFWL after the first read from a full FIFO,
to ensure that valid write data is written.
Figure 34. FIFO #2 Read and Write Operation in
Near-Full Region
46
543611-36
Share Link: 
