LH543621 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543621' PDF : 57 Pages View PDF
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CKA
R/WA
ENA
REQA
D0A - D35A
FF1
CKB
tRWH tRWS
t RWH
tRWS
tEH
t ES
tEH
t ES
tRQH tRQS
tRQH tRQS
tDH
tDS
tDH
tDS
t FWL
t FF
t FF
tRWH tRWS
tRWH tRWS
R/WB
tEH
t ES
tEH
t ES
ENB
tRQH tRQS
tRQH tRQS
REQB
tA
tA
t OH
t OH
D0B - D35B
PREVIOUS DATA
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. OEA is held HIGH.
3. OEB is held LOW.
4. tFWL (First Write Latency) - The first write following a full condition
may begin no earlier than tFWL after the first read from a full FIFO,
to ensure that valid write data is written.
Figure 33. FIFO #1 Read and Write Operation in
Near-Full Region
LH543611/21
543611-35
45
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