LPC1767 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'LPC1767' PDF : 79 Pages View PDF
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
[5] Applies to LPC1768/67/66/65/64/63.
[6] Applies to LPC1769 only.
[7] IRC running at 4 MHz; main oscillator and PLL disabled; PCLK = CCLK⁄8.
[8] BOD disabled.
[9] On pin VDD(REG)(3V3). IBAT = 530 nA. VDD(REG)(3V3) = 3.0 V; VBAT = 3.0 V; Tamb = 25 °C.
[10] On pin VBAT; IDD(REG)(3V3) = 630 nA; VDD(REG)(3V3) = 3.0 V; VBAT = 3.0 V; Tamb = 25 °C.
[11] On pin VBAT; VBAT = 3.0 V; Tamb = 25 °C.
[12] All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(3V3) = 3.3 V; Tamb = 25 °C.
[13] On pin VDDA; VDDA = 3.3 V; Tamb = 25 °C. The ADC is powered if the PDN bit in the AD0CR register is set to 1 and in Power-down mode
of the PDN bit is set to 0.
[14] The ADC is powered if the PDN bit in the AD0CR register is set to 1. See LPC17xx user manual UM10360_1.
[15] The ADC is in Power-down mode if the PDN bit in the AD0CR register is set to 0. See LPC17xx user manual UM10360_1.
[16] Vi(VREFP) = 3.3 V; Tamb = 25 °C.
[17] Including voltage on outputs in 3-state mode.
[18] VDD(3V3) supply voltages must be present.
[19] 3-state outputs go into 3-state mode in Deep power-down mode.
[20] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[21] To VSS.
[22] Includes external resistors of 33 Ω ± 1 % on D+ and D−.
10.1 Power consumption
400
IDD(Reg)(3V3)
(μA)
350
300
002aaf568
3.6 V
3.3 V
2.4 V
250
200
−40
−15
10
35
60
85
temperature (°C)
Fig 7.
Conditions: VDD(Reg)(3V3) = 3.3 V; BOD disabled.
Deep-sleep mode: typical regulator supply current IDD(Reg)(3V3) versus
temperature
LPC1769_68_67_66_65_64_63
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 5 April 2011
© NXP B.V. 2011. All rights reserved.
47 of 79
Share Link: 
