NXP Semiconductors
LPC2212/2214
16/32-bit ARM microcontrollers
Table 10. External memory interface dynamic characteristics
CL = 25 pF; Tamb = 40 °C.
Symbol Parameter
Conditions
Min
Common to read and write cycles
tCHAV
XCLK HIGH to address valid
-
time
tCHCSL XCLK HIGH to CS LOW time
-
tCHCSH XCLK HIGH to CS HIGH
-
time
tCHANV XCLK HIGH to address
-
invalid time
Read cycle parameters
tCSLAV
CS LOW to address valid
time
[1] −5
tOELAV
OE LOW to address valid
time
[1] −5
tCSLOEL
tam
CS LOW to OE LOW time
memory access time
−5
[2][3] (Tcy(CCLK) × (2 + WST1)) +
(−20)
tam(ibr)
memory access time (initial
burst-ROM)
[2][3] (Tcy(CCLK) × (2 + WST1)) +
(−20)
tam(sbr)
memory access time
(subsequent burst-ROM)
[2][4] Tcy(CCLK) + (−20)
th(D)
tCSHOEH
tOEHANV
data hold time
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
[5] 0
−5
−5
tCHOEL XCLK HIGH to OE LOW time
−5
tCHOEH XCLK HIGH to OE HIGH
−5
time
Write cycle parameters
tAVCSL
address valid to CS LOW
time
[1] Tcy(CCLK) − 10
tCSLDV
tCSLWEL
tCSLBLSL
tWELDV
tCSLDV
tWELWEH
CS LOW to data valid time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to data valid time
CS LOW to data valid time
WE LOW to WE HIGH time
−5
−5
−5
−5
−5
[2] Tcy(CCLK) × (1 + WST2) − 5
tBLSLBLSH BLS LOW to BLS HIGH time
[2] Tcy(CCLK) × (1 + WST2) − 5
tWEHANV
tWEHDNV
tBLSHANV
WE HIGH to address invalid
time
WE HIGH to data invalid time
BLS HIGH to address invalid
time
[2] Tcy(CCLK) − 5
[2] (2 × Tcy(CCLK)) − 5
[2] Tcy(CCLK) − 5
Typ Max
Unit
- 10
ns
- 10
ns
- 10
ns
- 10
ns
- +10
ns
- +10
ns
- +5
ns
--
ns
--
ns
--
ns
--
ns
- +5
ns
- +5
ns
- +5
ns
- +5
ns
--
ns
- +5
ns
- +5
ns
- +5
ns
- +5
ns
- +5
ns
-
Tcy(CCLK) × (1 +
ns
WST2) + 5
-
Tcy(CCLK) ×
ns
(1 + WST2) + 5
-
Tcy(CCLK) + 5
ns
-
(2 × Tcy(CCLK)) + 5 ns
-
Tcy(CCLK) + 5
ns
LPC2212_2214_4
Product data sheet
Rev. 04 — 3 January 2008
© NXP B.V. 2008. All rights reserved.
37 of 45