LPC2212 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
LPC2212
NXP Semiconductors.
'LPC2212' PDF : 45 Pages View PDF
NXP Semiconductors
LPC2212/2214
16/32-bit ARM microcontrollers
Table 10. External memory interface dynamic characteristics …continued
CL = 25 pF; Tamb = 40 °C.
Symbol Parameter
Conditions
Min
tBLSHDNV BLS HIGH to data invalid
time
[2] (2 × Tcy(CCLK)) − 5
tCHDV
XCLK HIGH to data valid
-
time
tCHWEL XCLK HIGH to WE LOW
-
time
tCHBLSL XCLK HIGH to BLS LOW
-
time
tCHWEH XCLK HIGH to WE HIGH
-
time
tCHBLSH XCLK HIGH to BLS HIGH
-
time
tCHDNV XCLK HIGH to data invalid
-
time
[1] Except on initial access, in which case the address is set up Tcy(CCLK) earlier.
[2] Tcy(CCLK) = 1⁄CCLK.
[3] Latest of address valid, CS LOW, OE LOW to data valid.
[4] Address valid to data valid.
[5] Earliest of CS HIGH, OE HIGH, address change to data invalid.
Typ Max
Unit
-
(2 × Tcy(CCLK)) + 5 ns
- 10
ns
- 10
ns
- 10
ns
- 10
ns
- 10
ns
- 10
ns
Table 11. Standard read access specifications
Access cycle
Max frequency
WST[1] setting
WST ≥ 0; round up to
integer
standard read
f
M
A
X
≤
----2-----+-----W-----S---T----1------
tRAM + 20 ns
WST 1 ≥ -t--R--t-A-c--My---(--C-+--C--2--L-0--K---)-n---s- – 2
standard write
f MAX ≤ t--W---1--R---+I--T---WE----+-S---T-5---2--n----s WST 2 ≥ -t-W-----R---I-t-T-c--Ey---(-–C----C-t--CL---YK---C-)----+-----5-
burst read - initial
f
MAX
≤
----2-----+-----W-----S---T----1-----
tINIT + 20 ns
WST 1 ≥ -t--I-N-t--c-I-y-T--(--C+---C--2-L--0-K----)n----s – 2
burst read - subsequent 3×
f
MAX
≤
----------------1----------------
tROM + 20 ns
N/A
Memory access time requirement
tRAM ≤ tcy(CCLK ) × (2 + WST 1) – 20 ns
tWRITE ≤ tcy(CCLK) × (1 + WST2) – 5 ns
tINIT ≤ tcy(CCLK ) × (2 + WST 1) – 20 ns
tROM ≤ tcy(CCLK ) – 20 ns
[1] See the LPC2114/2124/2212/2214 User Manual for a description of the WSTn bits.
LPC2212_2214_4
Product data sheet
Rev. 04 — 3 January 2008
© NXP B.V. 2008. All rights reserved.
38 of 45
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