LPC47M14X View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47M14X' PDF : 205 Pages View PDF
REGISTER
Device ID -
Hard wired
ADDRESS
0x20 R
DESCRIPTION
Chip Level, SMSC Defined
A read only register which provides
identification. Bits[7:0] = 0x5F when read.
device
STATE
C
Default = 0x5F
on VCC POR,
VTR POR,
SOFT RESET and
HARD RESET
Device Rev
0x21 R A read only register which provides device revision
C
information. Bits[7:0] = current revision when read.
Hard wired
= Current Revision
PowerControl
0x22 R/W Bit[0] FDC Power
C
Bit[1] Reserved
Default = 0x00
Bit[2] Game Port Power
on VCC POR,
Bit[3] Parallel Port Power
VTR POR,
Bit[4] Serial Port 1 Power
SOFT RESET and
HARD RESET
Bit[5] Serial Port 2 Power (Note 1)
Bit[6] Serial Port 3 Power
Bit[7] Reserved
Power Mgmt
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
0: Power Off or Disabled
1: Power On or Enabled
0x23 R/W Bit[0] FDC (see Note in the “FDC Power
C
Management” section.)
Bit[1] Reserved
Bit[2] Reserved
Bit[3] Parallel Port
Bit[4] Serial Port 1
Bit[5] Serial Port 2
Bit[6] Serial Port 3
Bit[7] Reserved (read as 0)
For each bit above (except Reserved)
=0
Intelligent Pwr Mgmt off
=1
Intelligent Pwr Mgmt on
OSC
0x24 R/W Bit[0] Reserved
C
Bit [1] PLL Control
Default = 0x44, on
VCC POR,
VTR POR and
HARD RESET
=0
PLL is on (backward Compatible)
=1
PLL is off
Bits[3:2] OSC
= 01 Osc is on, BRG clock is on.
= 10 Same as above (01) case.
= 00 Osc is on, BRG Clock Enabled.
= 11 Osc is off, BRG clock is disabled.
Bit [5:4] Reserved, set to zero
Bit [6] 16-Bit Address Qualification
=0
12-Bit Address Qualification
=1
16-Bit Address Qualification
Note: For normal operation, bit 6 should be set.
Bit[7] Reserved
SMSC DS – LPC47M14X
Page 157
Rev. 03/19/2001
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