LPC47N227-MN View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47N227-MN' PDF : 202 Pages View PDF
to the head unload state. The SRT (Step Rate Time) defines the time interval between adjacent step
pulses. Note that the spacing between the first and second step pulses may be shorter than the
remaining step pulses. The HLT (Head Load Time) defines the time between when the Head Load
signal goes high and the read/write operation starts. The values change with the data rate speed
selection and are documented in Table 26. The values are the same for MFM and FM.
The choice of DMA or non-DMA operations is made by the ND bit. When this bit is "1", the non-DMA
mode is selected, and when ND is "0", the DMA mode is selected. In DMA mode, data transfers are
signaled by the DMA request cycles. Non-DMA mode uses the RQM bit and the interrupt to signal data
transfers.
Configure
The Configure command is issued to select the special features of the FDC. A Configure command
need not be issued if the default values of the FDC meet the system requirements.
Table 26 – Drive Control Delays (ms)
HUT
SRT
2M 1M 500K 300K 250K 2M 1M 500K 300K 250K
0 64 128 256 426 512 4
8
16 26.7 32
14
8
16 26.7 32 3.75 7.5 15 25 30
.. ..
..
..
..
..
..
..
..
..
..
E 56 112 224 373 448 0.5
1
2 3.33 4
F 60 120 240 400 480 0.25 0.5
1 1.67 2
2M
00
64
01
0.5
02
1
..
..
7F
63
7F
63.5
HLT
1M
500K
300K
250K
128
256
426
512
1
2
3.3
4
2
4
6.7
8
..
..
..
.
126
252
420
504
127
254
423
508
Configure Default Values:
EIS - No Implied Seeks
EFIFO - FIFO Disabled
POLL - Polling Enabled
FIFOTHR - FIFO Threshold Set to 1 Byte
PRETRK - Pre-Compensation Set to Track 0
EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a
read or write command. Defaults to no implied seek.
EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byte-by-byte basis.
Defaults to "1", FIFO disabled. The threshold defaults to "1".
POLL - Disable polling of the drives. Defaults to "0", polling enabled. When enabled, a single interrupt is
generated after a reset. No polling is performed while the drive head is loaded and the head unload delay
has not expired.
64
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