LPC47N227-MN View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47N227-MN' PDF : 202 Pages View PDF
to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration
Registers for information on disabling, power down and changing the base address of the UARTs. The
interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic
"0" disables that UART's interrupt. The second UART also supports IrDA 1.2 (4Mbps), HP-SIR, ASK-IR
and Consumer IR infrared modes of operation.
Register Description
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial
ports are defined by the configuration registers (see Configuration section). The Serial Port registers are
located at sequentially increasing addresses above these base addresses. The LPC47N227 contains two
serial ports, each of which contain a register set as described below.
Table 28 - Addressing the Serial Port
DLAB* A2
A1
A0
REGISTER NAME
0
0
0
0 Receive Buffer (read)
0
0
0
0 Transmit Buffer (write)
0
0
0
1 Interrupt Enable (read/write)
X
0
1
0 Interrupt Identification (read)
X
0
1
0 FIFO Control (write)
X
0
1
1 Line Control (read/write)
X
1
0
0 Modem Control (read/write)
X
1
0
1 Line Status (read/write)
X
1
1
0 Modem Status (read/write)
X
1
1
1 Scratchpad (read/write)
1
0
0
0 Divisor LSB (read/write)
1
0
0
1 Divisor MSB (read/write
*Note: DLAB is Bit 7 of the Line Control Register
The following section describes the operation of the registers.
Receive Buffer Register (RB)
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted
and received first. Received data is double buffered; this uses an additional shift register to receive the
serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register.
The shift register is not accessible.
Transmit Buffer Register (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY
This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an
additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is
loaded from the Transmit Buffer when the transmission of the previous byte is complete.
Interrupt Enable Register (IER)
Address Offset = 1H, DLAB = 0, READ/WRITE
The lower four bits of this register control the enables of the five interrupt sources of the Serial Port
interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register.
Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. Disabling
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