LPC47N227-MN View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47N227-MN' PDF : 202 Pages View PDF
(GAP, WGATE and D0-D3) to "0", i.e all conventional mode.
Table 27 – Effects of WGATE and GAP Bits
PORTION OF
GAP 2
LENGTH OF WRITTEN BY
GAP2 FORMAT WRITE DATA
WGATE GAP
MODE
FIELD
OPERATION
0
0 Conventional
22 Bytes
0 Bytes
0
1 Perpendicular
22 Bytes
19 Bytes
(500 Kbps)
1
0 Reserved
22 Bytes
0 Bytes
(Conventional)
1
1 Perpendicular
41 Bytes
38 Bytes
(1 Mbps)
LOCK
In order to protect systems with long DMA latencies against older application software that can disable the
FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and
application software should refrain from using it. If an application calls for the FIFO to be disabled then the
CONFIGURE command should be used.
The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the
CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic
"1" all subsequent "software RESETS by the DOR and DSR registers will not change the previously set
parameters to their default values. All "hardware" RESET from the nPCI_RESET pin will set the LOCK bit
to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is
returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by
the command byte.
Enhanced DUMPREG
The DUMPREG command is designed to support system run-time diagnostics and application software
development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR
MODE command the eighth byte of the DUMPREG command has been modified to contain the additional
data from these two commands.
Compatibility
The LPC47N227 was designed with software compatibility in mind. It is a fully backwards- compatible
solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for
compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a
hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2
Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the
system BIOS.
SERIAL PORT (UART)
The LPC47N227 incorporates two full function UARTs. They are compatible with the NS16450, the 16450
ACE registers and the NS16C550A. The UARTS perform serial-to-parallel conversion on received
characters and parallel-to-serial conversion on transmit characters. The data rates are independently
programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1,
1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a
programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1
68
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