LPC47U33X View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47U33X
SMSC -> Microchip
'LPC47U33X' PDF : 252 Pages View PDF
Table 29 - Typical Values for Formatting
FORMAT SECTOR SIZE
N
SC
GPL1
GPL2
128
00
12
07
09
128
00
10
10
19
512
02
08
18
30
FM
1024
03
04
46
87
2048
04
02
C8
FF
5.25"
4096
05
01
C8
FF
Drives
...
...
256
01
12
0A
0C
256
01
10
20
32
512*
02
09
2A
50
MFM
1024
03
04
80
F0
2048
04
02
C8
FF
4096
05
01
C8
FF
...
...
128
0
0F
07
1B
3.5"
FM
256
1
09
0F
2A
Drives
512
2
05
1B
3A
256
1
0F
0E
36
MFM
512**
2
09
1B
54
1024
3
05
35
74
GPL1 = suggested GPL values in Read and Write commands to avoid splice point
between data field and ID field of contiguous sections.
GPL2 = suggested GPL value in Format A Track command.
*PC/AT values (typical)
**PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives.
NOTE: All values except sector size are in hex.
Control Commands
Control commands differ from the other
commands in that no data transfer takes place.
Three commands generate an interrupt when
complete: Read ID, Recalibrate, and Seek. The
other control commands do not generate an
interrupt.
the MA bit in Status Register 1 to "1", and
terminates the command.
The following commands will generate an
interrupt upon completion. They do not return
any result bytes. It is highly recommended that
control commands be followed by the Sense
Interrupt Status command. Otherwise, valuable
interrupt status information will be lost.
Read ID
The Read ID command is used to find the
present position of the recording heads. The
FDC stores the values from the first ID field it is
able to read into its registers. If the FDC does
not find an ID address mark on the diskette after
the second occurrence of a pulse on the
nINDEX pin, it then sets the IC code in Status
Register 0 to "01" (abnormal termination), sets
Recalibrate
This command causes the read/write head
within the FDC to retract to the track 0 position.
The FDC clears the contents of the PCN counter
and checks the status of the nTRK0 pin from the
FDD. As long as the nTRK0 pin is low, the DIR
pin remains 0 and step pulses are issued.
When the nTRK0 pin goes high, the SE bit in
Status Register 0 is set to "1" and the command
64
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