LRS1302 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1302' PDF : 61 Pages View PDF
SHARP
LRS13023
19
4.8 Byte Write Suspend Command
The Byte Write Suspend command allows byte write
interruption to read data in other flash memory
locations. Once the byte write process starts, writing
the Byte Write Suspend command requests that the
WSM suspend the byte write sequence at a
predetermined point in the algorithm. The device
continues to output status register data when read
after the Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can determine
when the byte write operation has been suspended
(both will be set to “1”). Specification twHRHl defines
the byte write suspend latency.
At this point, a Read Array command can be written to
read data from locations other than that which is
suspended. The only other valid commands while byte
write is suspended are Read Status Register and Byte
Write Resume. After Byte Write Resume command is
written to the flash memory, the WSM will continue
the byte write process. Status register bits SR.2 and
SR7 will automatically clear. After the Byte Write
Resume command is written, the device automatically
outputs status register data when read (see Figure 7).
VP, must remain at V,, (the same VP, level used for
byte write) while in byte write suspend mode. m
must also remain at VrH or V, (the same Rp level
used for byte write).
4.9 Set Block and Master Lock-Bit Commands
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a
master lock-bit. The block lock-bits gate program and
erase operations while the master lock-bit gates
block-lock bit modification. With the master lock-bit
not set, individual block lock-bits can be set using the
Set Block Lock-Bit command. The Set Master Lock-Bit
zommand, in conjunction with i@=V,, sets the
master lock-bit. After the master lock-bit is set,
subsequent setting of block lock-bits requires both the
Set Block Lock-Bit command and V, on the m pin.
see Table 6 for a summary of hardware and software
write protection options.
Set block lock-bit and master lock-bit are executed by a
two-cycle command sequence. The set block or master
lock-bit setup along with appropriate block or device
address is written followed by either the set block
lock-bit confirm (and an address within the block to be
locked) or the set master lock-bit confirm (and any
device address). The WSM then controls the set
lock-bit algorithm. After the sequence is written, the
device automatically outputs status register data when
read (see Figure 8). The CPU can detect the completion
of the set lock-bit event by analyzing status register bit
SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUT will remain in read status register mode until a
new comman d is issued.
This two-step sequence of set-up followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Master Lock-Bit command
will result in z&us register bits SR.4 and SR.5 being
set to “1”. Also; reliable operations occur only when
vcc=vccl and ‘V+=VPPH. ln the absence of this high
voltage, lock-bit contents are .protected against
alteration.
:
I
A successful set block lock-bit .operation requires that
the master lo&bit be cleared or, if the master lock-bit
is set, that Rp=V&. Eit is attempted with the master
lock-bit set and; RP=VIH, SR.l and SR.4 will be set to
“1” and the operation -will fail. Set block lock-bit
operations while ~V,,<RP<V,
:produce spurious
results and should not be attempted. A successful set
master lock-bit operation requires that m=V,. If it is
attempted with Rp=V,,, SR.l and SR.4 will be set to
“1” and the operation -will fail. Set master lock-bit
operations with VIHcRR<V,
produce spurious
results and should not be attempted.
Share Link: 
