LRS1302 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1302' PDF : 61 Pages View PDF
SHARP
LRS13023
21
WSMS
7
1 ESS
6
1 ECLBS
5
Table 7. Status Register Definition
( BWSLBS ( VPRS
BWSS
4
3
2
NOTES:
DPS I
R
1
0
SR.7 = WRITE STATE MACHINE
1= Ready
0 = Busy
STATUS
Check SR.7 to determine block erase, byte write, or
lock-bit configuration compIetion.
SR6-0 are invalid while SR.7=“0”.
SR.6 = ERASE SUSPEND STATUS
1= Block Erase Suspended
0 = Block Erase in Progress/Completed
If both SR.5 and SR.4 are “1”s after a block erase or
lock-bit configuration attempt, an improper command
sequence was entered.
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS
1= Error in Block Erasure or Clear Lock-Bi is
0 = Successful Block Erase or Clear Lock-Bits
SR.4 = BYTE WRITE AND SET LOCK-BITeSTATUS
1 = Error in Byte Write or Set Master/Block Lock-Bit
0 = Successful Byte Write or Set Master/Block
Lock-Bit
SR.3 = V,, STATUS
1 = VP, Low Detect, Operation Abort
O=V,,OK
SR.2 = BYTE WRITE SUSPEND STATUS
1 = Byte Write Suspended
0 = Byte Write in Progress/Completed
SR.l = DEVICE PROTECT STATUS
1 = Master Lock-Bit, Block Lock-Bit and/or p Lock
Detected, Operation Abort
0 = Unlock
SR.3 does not provide a continuous indication of VP,
level. The WSM interrogates and indicates the V,, level
only after Block Erase, Byte Write, Set Block/Master
Lock-Bit, or Clear Block Lock-Bits command sequences.
SR.3 is not guaranteed to reports accurate feedback only
when V,,=V,,,.
SR.1 does not provide a continuous indication of master
and block lock-bit values. The WSM interrogates the
master lock-bit, block lock-bit, and RP only after Block
Erase, Byte Write, or Lock-Bit configuration command
sequences. It informs the system, depending on the
attempted operation, if the block lock-bit is set, master
lock-bit is set, and/or RP is not V,,. Reading the block
lock and master lock configuration codes after writing
the Read Identifier Codes command indicates master
and block lock-bit status.
SR.0 is reserved for future use and should be masked
out when polling the status register.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
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