LRS1383 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1383' PDF : 114 Pages View PDF
LRS1383
27
13. AC Electrical Characteristics for SRAM
13.1 AC Test Conditions
Input pulse level
Input rise and fall time
Input and Output timing Ref. level
Output load
Note:
1. Including scope and socket capacitance.
0.4V to 2.2V
5ns
1.5 V
1TTL + CL (30pF)(1)
13.2 Read Cycle
Symbol
Parameter
(TA = -25°C to +85°C, S-VCC = 2.7V to 3.3V)
Notes Min. Max. Unit
tRC Read Cycle Time
70
ns
tAA Address access time
70
ns
tACE1 Chip enable access time (S-CE1)
70
ns
tACE2 Chip enable access time (S-CE2)
70
ns
tBE Byte enable access time
70
ns
tOE Output enable to output valid
40
ns
tOH Output hold from address change
10
ns
tLZ1 S-CE1 Low to output active
1
10
ns
tLZ2 S-CE2 High to output active
1
10
ns
tOLZ S-OE Low to output active
1
5
ns
tBLZ S-UB or S-LB Low to output active
1
5
ns
tHZ1 S-CE1 High to output in High-Z
1
0
25
ns
tHZ2 S-CE2 Low to output in High-Z
1
0
25
ns
tOHZ S-OE High to output in High-Z
1
0
25
ns
tBHZ S-UB or S-LB High to output in High-Z
1
0
25
ns
Note:
1. Active output to High-Z and High-Z to output active tests specified for a ±200mV transition from steady state levels into
the test load.
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