LRS1383 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1383' PDF : 114 Pages View PDF
LRS1383
34
15. Notes
This product is a stacked CSP package that a 32M (x16) bit Flash Memory and a 8M (x16) bit SRAM are assembled into.
- Supply Power
Maximum difference (between F-VCC and S-VCC) of the voltage is less than 0.3V.
- Power Supply and Chip Enable of Flash Memory and SRAM (F-CE, S-CE1, S-CE2)
S-CE1 should not be “low” and S-CE2 should not be “high” when F-CE is “low” simultaneously.
If the two memories are active together, possibly they may not operate normally by interference noises or data collision
on DQ bus.
Both F-VCC and S-VCC are needed to be applied by the recommended supply voltage at the same time expect SRAM
data retention mode.
- Power Up Sequence
When turning on Flash memory power supply, keep F-RST “low”. After F-VCC reaches over 2.7V, keep F-RST “low”
for more than 100nsec.
- Device Decoupling
The power supply is needed to be designed carefully because one of the SRAM and the Flash Memory is in standby
mode when the other is active. A careful decoupling of power supplies is necessary between SRAM and Flash
Memory. Note peak current caused by transition of control signals (F-CE, S-CE1, S-CE2).
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