Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

LT3992EFE View Datasheet(PDF) - Linear Technology

Part Name
Description
MFG CO.
'LT3992EFE' PDF : 36 Pages View PDF
LT3992
Applications Information
LT3992
R1
TJ
VNEG
GND
3992 F20
Figure 20. Circuit to Extend the TJ Pin Operating Range
30k
TJ
LT3992
330pF
D4
CLKOUT
GND
D3
0.1µF
D3, D4: ZETEX BAT54S
3992 F21
Figure 21. Circuit to Generate the Negative Voltage Rail to
Extend the TJ Pin Operating Range
Generating a Negative Regulated Voltage
The simple charge pump circuit in Figure 21 uses the
CLKOUT pin output to generate a negative voltage, elimi-
nating the need for an external regulated supply. Surface
mount capacitors and dual-package Schottky diodes
minimize the board area needed to implement the nega-
tive voltage supply.
As a safeguard, the LT3992 has an additional thermal
shutdown threshold set at a typical value of 163°C for each
channel. Each time the threshold is exceeded, a power on
sequence for that channel will be initiated. The sequence
will then repeat until the thermal overload is removed.
It should be noted that the TJ pin voltage represents
a steady-state temperature and should not be used to
guarantee that maximum junction temperatures are
not exceeded. Instantaneous power along with thermal
gradients and time constants may cause portions of the
die to exceed maximum ratings and thermal shutdown
thresholds. Be sure to calculate die temperature rise for
steady state (>1Min) as well as impulse conditions.
the CLKOUT pin, resulting in an output synchronization
clock signal phase delay. Figures 22 and 23 show the im-
pact of capacitive loading on the CLKOUT signal rise and
fall times. Note that a typical 10:1 150MHz oscilloscope
probe contributes significant capacitance to the CLKOUT
node, necessitating a low capacitance probe for accurate
measurements. Applications requiring CLKOUT to generate
the negative supply voltage and provide the synchroniza-
tion clock to other regulators may benefit from buffering
CLKOUT prior to the charge pump circuitry.
Other Linear Technology Publications
Application Notes 19, 35 and 44 contain more detailed
descriptions and design information for buck regulators
and other switching regulators. The LT1376 data sheet
has a more extensive discussion of output ripple, loop
compensation and stability testing. Design Note DN100
shows how to generate a dual (+ and –) output supply
using a buck regulator.
500mV/DIV
CHARGE PUMP
SCOPE PROBE: 15pF
SYNCHRONIZED LT3992
RT/SYNC PIN
FET PROBE: 2pF
40ns/DIV
FREQUENCY: 1.000MHz
3992 F22
Figure 22. CLKOUT Rise Time
CHARGE PUMP
500mV/DIV
FET PROBE: 2pF
SCOPE PROBE: 15pF
SYNCHRONIZED
LT3992 RT/SYNC PIN
CLKOUT Capacitive Loading
A minor drawback to generating a negative rail from the
CLKOUT pin is that the charge pump adds capacitance to
20ns/DIV
FREQUENCY: 1.000MHz
3992 F23
Figure 23. CLKOUT Fall Time
3992fa
28
For more information www.linear.com/LT3992
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]