LTC1608AIG View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1608AIG' PDF : 20 Pages View PDF
LTC1608
TYPICAL PERFOR A CE CHARACTERISTICS
Intermodulation Distortion
0
fSAMPLE = 500kHz
–20
fIN1 = 96.56kHz
fIN2 = 99.98kHz
–40
–60
–80
–100
–120
–140
0
50 100 150 200 250
FREQUENCY (kHz)
1608 G07
Power Supply Feedthrough
vs Ripple Frequency
0
fSAMPLE = 500kHz
–20 VRIPPLE = 10mV
–40
–60
–80
–100
–120
AVDD
VSS
–140
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
1608 G08
Input Common Mode Rejection
vs Input Frequency
80
70
60
50
40
30
20
10
0
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
1608 G14a
PI FU CTIO S
AIN+ (Pin 1): Positive Analog Input. The ADC converts the
difference voltage between AIN+ and AIN– with a differen-
tial range of ±2.5V. AIN+ has a ±2.5V input range when
AIN– is grounded.
AIN– (Pin 2): Negative Analog Input. Can be grounded, tied
to a DC voltage or driven differentially with AIN+.
VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with
2.2µF tantalum in parallel with 0.1µF ceramic.
REFCOMP (Pin 4): 4.375V (Nominal) Reference Compen-
sation Pin. Bypass to AGND with 22µF tantalum in parallel
with 0.1µF ceramic. This is not recommended for use as
an external reference due to part-to-part output voltage
variations and glitches that occur during the conversion.
AGND (Pins 5 to 8): Analog Grounds. Tie to analog ground
plane.
DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGND
with 10µF tantalum in parallel with 0.1µF ceramic.
DGND (Pin 10): Digital Ground for Internal Logic. Tie to
analog ground plane.
D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15
is the Most Significant Bit.
BUSY (Pin 27): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data is
valid on the rising edge of BUSY.
OGND (Pin 28): Digital Ground for Output Drivers.
OVDD (Pin 29): Digital Power Supply for Output Drivers.
Bypass to OGND with 10µF tantalum in parallel with 0.1µF
ceramic.
RD (Pin 30): Read Input. A logic low enables the output
drivers when CS is low.
CONVST (Pin 31): Conversion Start Signal. This active
low signal starts a conversion on its falling edge when CS
is low.
CS (Pin 32): The Chip Select Input. Must be low for the ADC
to recognize CONVST and RD inputs.
SHDN (Pin 33): Power Shutdown. Drive this pin low with
CS low for nap mode. Drive this pin low with CS high for
sleep mode.
VSS (Pin 34): – 5V Negative Supply. Bypass to AGND with
10µF tantalum in parallel with 0.1µF ceramic.
AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic.
AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic and
connect this pin to Pin 35 with a 10Ω resistor.
6
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