LTC1608AIG View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1608AIG' PDF : 20 Pages View PDF
LTC1608
APPLICATIO S I FOR ATIO
AIN+
SAMPLE
CSMPL
HOLD
AIN–
SAMPLE
CSMPL
HOLD
+CDAC
+VDAC
–CDAC
ZEROING SWITCHES
HOLD
HOLD
+
COMP
–
–VDAC
SAR
16
OUTPUT
LATCHES
•
•
•
D15
D0
1608 F01
Figure 1. Simplified Block Diagram
compared with the binary-weighted charges supplied by
the differential capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion, the
differential DAC output balances the AIN+ and AIN– input
charges. The SAR contents (a 16-bit data word) which
represent the difference of AIN+ and AIN– are loaded into
the 16-bit output latches.
DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a con-
version.
Internal Clock
The A/D converter has an internal clock that runs the A/D
conversion. The internal clock is factory trimmed to achieve
a typical conversion time of 1.45µs and a maximum
conversion time of 1.8µs over the full temperature range.
No external adjustments are required. The guaranteed
maximum acquisition time is 400ns. In addition, a through-
put time (acquisition + conversion) of 2µs and a minimum
sampling rate of 500ksps are guaranteed.
3V Input/Output Compatible
The LTC1608 operates on ±5V supplies, which makes the
device easy to interface to 5V digital systems. This device
can also talk to 3V digital systems: the digital input pins
(SHDN, CS, CONVST and RD) of the LTC1608 recognize
3V or 5V inputs. The LTC1608 has a dedicated output
supply pin (OVDD) that controls the output swings of the
digital output pins (D0 to D15, BUSY) and allows the part
to talk to either 3V or 5V digital systems. The output is
two’s complement binary.
Power Shutdown
The LTC1608 provides two power shutdown modes, Nap
and Sleep, to save power during inactive periods. The Nap
mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up time
from Nap to active is 200ns. In Sleep mode, all bias
currents are shut down and only leakage current remains
(about 1µA). Wake-up time from Sleep mode is much
longer since the reference circuit must power up and
settle. Sleep mode wake-up time is dependent on the
value of the capacitor connected to the REFCOMP (Pin 4).
The wake-up time is 80ms with the recommended 22µF
capacitor.
Shutdown is controlled by Pin 33 (SHDN). The ADC is in
shutdown when SHDN is low. The shutdown mode is
selected with Pin 32 (CS). When SHDN is low, CS low
selects nap and CS high selects sleep.
SHDN
t3
CS
1608 F02a
Figure 2a. Nap Mode to Sleep Mode Timing
SHDN
t4
CONVST
1608 F02b
Figure 2b. SHDN to CONVST Wake-Up Timing
8
Share Link: 
