LTC1960 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1960' PDF : 28 Pages View PDF
LTC1960
OPERATION
1-Byte SPI Write Format:
bit 7........byte 1..........bit 0
MOSI
D0 D1 D2 X A0 A1 A2 0
MISO
X D0 D1 D2 X A0 A1 A2
Charger Write Address:
A[2:0] = b111
Charger Write Data:
D2 = X
D1 = CHARGE_BAT2
D0 = CHARGE_BAT1
PowerPath Write Address:
A[2:0] = b110
PowerPath Write Data:
D2 = POWER_BY_DC
D1 = POWER_BY_BAT2
D0 = POWER_BY_BAT1
2-Byte SPI Write Format:
bit 7........byte 1..........bit 0
bit 7..........byte 2............bit 0
MOSI
D0 D1 D2 D3 D4 D5 D6 1
D7 D8 D9 D10 A0 A1 A2 0
MISO
X D0 D1 D2 D3 D4 D5 D6
1 D7 D8 D9 D10 A0 A1 A2
IDAC Write Address:
A[2:0] = b000
IDAC Data Bits D9-D0:
IDAC value data (MSB-LSB)
IDAC Data Bit D10 :
Normal mode = 0, low current mode = 1 (Dual battery charging is disabled)
VDAC Write Address:
A[2:0] = b001
VDAC Data Bits D10-D0:
VDAC value (MSB-LSB)
Subsequent SPI communication is inhibited until after the addressed DAC is finished loading. It is recommended that
the master transmit all zeros until MISO goes low. This handshaking procedure is illustrated in Figure 1.
SSB
SCK
MOSI
MISO
BYTE 1
BYTE 2
Figure 1. SPI Write to VDAC of Data = b101_0101_0101
1960 F01
1960fb
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