LTC2190 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2190' PDF : 28 Pages View PDF
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
CONVERTER OPERATION
The LTC2192/LTC2191/LTC2190 are low power, 2-channel,
16-bit, 65/40/25Msps A/D converters that are powered
by a single 1.8V supply. The analog inputs should be
driven differentially. The encode input can be driven dif-
ferentially or single ended for lower power consumption.
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs one bit at a time
(1-lane mode), two bits at a time (2-lane mode) or four
bits at a time (4‑lane mode). Many additional features can
be chosen by programming the mode control registers
through a serial SPI port.
ANALOG INPUT
The analog inputs are differential CMOS sample-and-
hold circuits (Figure 2). The inputs should be driven
differentially around a common mode voltage set by the
VCM1 or VCM2 output pins, which are nominally VDD/2.
For the 2V input range, the inputs should swing from
VCM – 0.5V to VCM + 0.5V. There should be 180° phase
difference between the inputs.
The two channels are simultaneously sampled by a shared
encode circuit (Figure 2).
Single-Ended Input
For applications less sensitive to harmonic distortion, the
AIN+ input can be driven singled ended with a 1VP-P signal
centered around VCM. The AIN– input should be connected
to VCM. With a singled-ended input the harmonic distortion
and INL will degrade, but the noise and DNL will remain
unchanged.
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
also limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with VCM, setting the A/D input at its optimal
LTC2192
VDD
10Ω
AIN+
VDD
10Ω
AIN–
VDD
CPARASITIC
1.8pF
CPARASITIC
1.8pF
RON
CSAMPLE
5pF
15Ω
CSAMPLE
RON 5pF
15Ω
ENC+
1.2V
10k
ENC–
10k
1.2V
219210 F02
Figure 2. Equivalent Input Circuit. Only One of Two Analog Channels Is Shown
219210p
17
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