LTC2259-16 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2259-16' PDF : 28 Pages View PDF
LTC2259-16
PIN FUNCTIONS
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0 to D15 (Pins 35, 36, 17-24, 29-34): Digital Outputs.
D15 is the MSB. D0 is the LSB.
CLKOUT– (Pin 27): Inverted Version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the digital outputs by programming the mode
control registers.
DOUBLE-DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0_1 to D14_15 (Pins 36,18, 20, 22, 24, 30, 32, 34):
Double-Data Rate Digital Outputs. Two data bits are multi-
plexed onto each output pin. The even data bits (D0, D2, D4,
D6, D8, D10, D12, D14) appear when CLKOUT+ is low. The
odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear
when CLKOUT+ is high.
CLKOUT– (Pin 27): Inverted Version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling and ris-
ing edges of CLKOUT+. The phase of CLKOUT+ can also
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 19, 21, 23, 29, 31, 33, 35): Do not con-
nect these pins.
DOUBLE-DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1–/D0_1+ to D14_15–/D14_15+ (Pins 35/36, 17/18,
19/20, 21/22, 23/24, 29/30, 31/32, 33/34): Double-Data
Rate Digital Outputs. Two data bits are multiplexed onto
each differential output pair. The even data bits (D0, D2,
D4, D6, D8, D10, D12, D14) appear when CLKOUT+ is low.
The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15)
appear when CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 27/28): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
225916f
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