LTC2259-16 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2259-16' PDF : 28 Pages View PDF
LTC2259-16
FUNCTIONAL BLOCK DIAGRAM
AIN+
INPUT
FIRST PIPELINED
SECOND PIPELINED
THIRD PIPELINED
FOURTH PIPELINED
FIFTH PIPELINED
VDD
AIN–
S/H
ADC STAGE
ADC STAGE
ADC STAGE
ADC STAGE
ADC STAGE
GND
VCM
0.1μF
VDD/2
VREF
1μF
1.25V
REFERENCE
RANGE
SELECT
SHIFT REGISTER
AND CORRECTION
REF
SENSE
BUF
REFH
REFL INTERNAL CLOCK SIGNALS
DIFF
CLOCK/DUTY
MODE
REF
CYCLE
CONTROL
AMP
CONTROL
REGISTERS
REFH 0.1μF
2.2μF
REFL
ENC+ ENC–
0.1μF
0.1μF
PAR/SER CS SCK SDI SDO
Figure 1. Functional Block Diagram
OVDD
OUTPUT
DRIVERS
D15
•
•
•
D0
CLKOUT+
CLKOUT–
OGND 225916 F01
APPLICATIONS INFORMATION
CONVERTER OPERATION
The LTC2259-16 is a low power 16-bit 80Msps A/D
converter that is powered by a single 1.8V supply. The
analog inputs should be driven differentially. The encode
input can be driven differentially, or single ended for lower
power consumption. The digital outputs can be CMOS,
double-data rate CMOS (to halve the number of output
lines), or double-data rate LVDS (to reduce digital noise
in the system.) Many additional features can be chosen by
programming the mode control registers through a serial
SPI port. See the Serial Programming Mode section.
ANALOG INPUT
The analog input is a differential CMOS sample-and-hold
circuit (Figure 2). The inputs should be driven differentially
around a common mode voltage set by the VCM output
pin, which is nominally VDD/2. For the 2V input range, the
inputs should swing from VCM – 0.5V to VCM + 0.5V. There
should be 180° phase difference between the inputs.
LTC2259-16
VDD
10Ω
AIN+
VDD
10Ω
AIN–
VDD
CPARASITIC
1.8pF
CPARASITIC
1.8pF
RON
CSAMPLE
3.5pF
25Ω
CSAMPLE
RON 3.5pF
25Ω
ENC+
ENC–
1.2V
10k
10k
1.2V
Figure 2. Equivalent Input Circuit
225916 F02
225916f
13
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