LTC2259-16 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2259-16' PDF : 28 Pages View PDF
LTC2259-16
APPLICATIONS INFORMATION
Phase-Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double-data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
setup-and-hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2259-16 can also phase shift the CLKOUT+/CLK-
OUT– signals by serially programming mode control
register A2. The output clock can be shifted by 0°, 45°,
90° or 135°. To use the phase shifting feature the clock
duty cycle stabilizer must be turned on. Another con-
trol register bit can invert the polarity of CLKOUT+ and
CLKOUT–, independently of the phase shift. The combina-
tion of these two features enables phase shifts of 45° up
to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A4. Note that when the analog input is
outside the normal operating range the two LSBs (D1,
D0) can change and should be ignored.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
D15-D0
(OFFSET BINARY)
>1.000000V
+0.999970V
+0.999939V
+0.999909V
+0.999978V
1111 1111 1111 11XX
1111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1101
1111 1111 1111 1100
+0.000030V
+0.000000V
+0.000030V
+0.000061V
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
–0.999878V
–0.999909V
–0.999939V
–1.000000V
< –1.000000V
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 00XX
Note: X means data could be 1 or 0.
D15-D0
(2’s COMPLEMENT)
0111 1111 1111 11XX
0111 1111 1111 1111
0111 1111 1111 1110
0111 1111 1111 1101
0111 1111 1111 1100
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1000 0000 0000 0011
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
1000 0000 0000 00XX
ENC+
18
D0-D13, OF
CLKOUT+
PHASE
SHIFT
0°
MODE CONTROL BITS
CLKINV CLKPHASE1 CLKPHASE0
0
0
0
45°
0
0
1
90°
0
1
0
135°
0
1
1
180°
1
0
0
225°
1
0
1
270°
1
1
0
315°
1
1
1
225916 F14
Figure 14. Phase-Shifting CLKOUT
225916f
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