LTC3778 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC3778' PDF : 24 Pages View PDF
LTC3778
APPLICATIO S I FOR ATIO
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The ITH pin external components shown in Figure 7
will provide adequate compensation for most applica-
tions. For a detailed explanation of switching control loop
theory see Linear Technology Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: VIN = 7V to 28V (15V nominal), VOUT = 2.5V
±5%, IOUT(MAX) = 10A, f = 250kHz. First, calculate the
timing resistor with VON = VOUT:
( )( ) RON =
1
= 400kΩ
250kHz 10pF
and choose the inductor for about 40% ripple current at
the maximum VIN:
( )( )( ) L =
2.5V
250kHz 0.4
10A
1−
2.5V
28V
=
2.3µH
Selecting a standard value of 1.8µH results in a maximum
ripple current of:
( )( ) ∆IL =
2.5V
250kHz 1.8µH
1–
2.5V
28V
=
5.1A
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (RDS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX),
θJA = 40°C/W) yields a nominal sense voltage of:
VSNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV
Tying VRNG to 1.1V will set the current sense voltage range
for a nominal value of 110mV with current limit occurring
at 146mV. To check if the current limit is acceptable,
assume a junction temperature of about 80°C above a
70°C ambient with ρ150°C = 1.5:
( )( ) ( ) ILIMIT ≥
146mV
1.5 0.010Ω
+ 1 5.1A
2
= 12A
and double check the assumed TJ in the MOSFET:
( ) ( )( ) PBOT
=
28V – 2.5V
28V
12A
2
1.5
0.010Ω
= 1.97W
TJ = 70°C + (1.97W)(40°C/W) = 149°C
Because the top MOSFET is on for such a short time, an
Si4884 RDS(ON)(MAX) = 0.0165Ω, CRSS = 100pF will be
sufficient. Checking its power dissipation at current limit
with ρ100°C = 1.4:
( ) ( )( ) PTOP
=
2.5V
28V
2
12A 1.4
0.0165Ω
+
(1.7)(28V)2( )( 12A 100pF)(250kHz)
= 0.30W + 0.40W = 0.7W
TJ = 70°C + (0.7W)(40°C/W) = 98°C
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
CIN is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR of
0.013Ω to minimize output voltage changes due to induc-
tor ripple current and load steps. The ripple voltage will be
only:
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (5.1A) (0.013Ω) = 66mV
However, a 0A to 10A load step will cause an output
change of up to:
∆VOUT(STEP) = ∆ILOAD (ESR) = (10A) (0.013Ω) = 130mV
An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 7.
3778f
17
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