LTC3778 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC3778' PDF : 24 Pages View PDF
LTC3778
APPLICATIO S I FOR ATIO
CSS
0.1µF
LTC3778
1 RUN/SS
20
BOOST
2 VON
RPG
R3
11k
R4
39k
100k 3 PGOOD
19
TG
18
SW
CC1
500pF
RC
20k
4 VRNG
5 ITH
SENSE+ 17
SENSE– 16
CC2
100pF
CON, 0.01µF
R1
12.7k
R2
40.2k
RON
400k
6 FCB
15
PGND
7 SGND
14
BG
8 ION
13
DRVCC
9 VFB
12
INTVCC
10 EXTVCC
11
VIN
DB
CMDSH-3
CB
0.22µF
CVCC
4.7µF
RF
1Ω
CF
0.1µF
M1
Si4884
L1, 1.8µH
CIN
10µF
35V
×3
VIN
5V TO 28V
VOUT
2.5V
10A
M2
Si4874
D1
B340A
+ COUT1-2
180µF
4V
×2
COUT3
22µF
6.3V
X7R
CIN: UNITED CHEMICON THCR60EIHI06ZT
COUT1-2: CORNELL DUBILIER ESRE181E04B
L1: SUMIDA CEP125-1R8MC-H
3778 F07
Figure 7. Design Example: 2.5V/10A at 250kHz
Active Voltage Positioning
Active voltage positioning (also termed load “deregula-
tion” or droop) describes a technique where the output
voltage varies with load in a controlled manner. It is useful
in applications where rapid load steps are the main cause
of error in the output voltage. By positioning the output
voltage at or above the regulation point at zero load, and
below the regulation point at full load, one can use more
of the error budget for the load step. This allows one to
reduce the number of output capacitors by relaxing the
ESR requirement.
For example, in a 20A application, six 0.015Ω capacitors
are required in parallel to keep the output voltage within a
100mV tolerance:
( )
±20A
1
6
0.015Ω
= ±50mV = 100mV
Using active voltage positioning, the same specification
can be met with only three capacitors. In this case, the load
step will cause an output voltage change of:
( ) ( ) ∆VOUT(STEP) =
20A
1
3
0.015Ω
= 100mV
By positioning the output voltage at the regulation point at
no load, it will drop 100mV below the regulation point after
the load step. However, when the load disappears or the
output is stepped from 20A to 0A, the 100mV is recovered.
This way, a total of 100mV change is observed on VOUT in
all conditions, whereas a total of ±100mV or 200mV is
seen on VOUT without voltage positioning while using only
three output capacitors.
Implementing active voltage positioning requires setting a
precise gain between the sensed current and the output
voltage. Because of the variability of MOSFET on-resis-
tance, it is prudent to use a sense resistor with active
voltage positioning. In order to minimize power lost in this
resistor, a low value of 0.002Ω is chosen. The nominal
sense voltage will now be:
VSNS(NOM) = (0.002Ω)(20A) = 40mV
To maintain a reasonable current limit, the voltage on the
VRNG pin is reduced to 0.5V by connecting it to a resistor
divider from INTVCC, corresponding to a 50mV nominal
sense voltage.
Next, the gain of the LTC3778 error amplifier must be
determined. The change in ITH voltage for a corresponding
change in the output current is:
3778f
18
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