LTC5587IDD View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC5587IDD' PDF : 20 Pages View PDF
LTC5587
APPLICATIONS INFORMATION
The total noise at the ADC output is dominated by the
output noise of the detector, and the sampling noise
is insignificant. The peak-to-peak output noise is also
almost independent of the sample rate. Figure 13 shows
the peak-to-peak noise at the ADC output as a function
of the RF input level for a CW RF input. Increasing CFILT
from 1000pF to 0.01μF gives roughly 2x to 3x lower noise
over input power.
40
35
30
25
20
15
10
5
0
–40
0.6
TA = 25°C
fSMPL = 500ksps 0.525
0.45
0.375
CFILT = 1000pF
0.3
0.225
CFILT = 0.01μF
0.15
0.075
–30 –20 –10
0
RF INPUT POWER (dBm)
0
10
5587 F13
Figure 13. Peak-to-Peak Noise at ADC Output vs RF Input Power
Serial Interface
The LTC5587 communicates with microcontrollers, DSPs
and other external circuitry via a 3-wire interface. Figure 14
shows the operating sequence of the serial interface.
Data Transfer
A rising CONV edge starts a conversion and disables SDO.
After the conversion, the ADC automatically goes into
sleep mode, drawing only leakage current. CONV going
low enables SDO and clocks out the MSB bit, B11. SCK
then synchronizes the data transfer with each bit being
transmitted on the falling SCK edge and can be captured
on the rising SCK edge. After completing the data transfer,
if further SCK clocks are applied with CONV low, SDO will
output zeros indefinitely (see Figure 14). For example,
16-clocks at SCK will produce the 12-bit data and four
trailing zeros on SDO.
Sleep Mode
The LTC5587 ADC enters sleep mode to save power after
each conversion if CONV remains high. In sleep mode, all
bias currents are shut down and only leakage currents
remain (about 0.1μA). The sample-and-hold is in hold
mode while the ADC is in sleep mode. The ADC returns
to sample mode after the falling edge of CONV during
power-up.
Exiting Sleep Mode and Power-Up Time
By taking CONV low, the ADC powers up and acquires an
input signal completely after the acquisition time (tACQ).
After tACQ, the ADC is ready to perform a conversion again
by a rising edge on CONV.
CONV
SCK
SDO
BY TAKING CONV LOW, THE DEVICE POWERS UP
AND ACQUIRES AN INPUT ACCURATELY AFTER tACQ
tCONV
SLEEP MODE
RECOMMENDED HIGH OR LOW
t2
1
2
Hi-Z STATE
t3
t4
B11
B10
(MSB)
t1
tTHROUGHPUT
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
t6
3
4
t5
B9
tACQ
9
10 11 12
t7
t8
B3 B2 B1 B0*
5587 F14
Figure 14. LTC5587 Serial Interface Timing Diagram
5587f
17
Share Link: 
