M34C02-LDW1G View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M34C02-LDW1G' PDF : 31 Pages View PDF
Device operation
M34C02-W, M34C02-L, M34C02-R
3.5
Memory Addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the Device Select Code,
shown in Table 2 (on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable
āAddressā (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b; to address the Protection Register, it is 0110b.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the Device Select code, it deselects itself from the bus, and goes into Stand-by mode.
Table 3. Operating Modes
Mode
RW bit WC(1)
Bytes
Initial Sequence
Current Address Read 1
X
1 START, Device Select, RW = 1
Random Address
Read
0
X
START, Device Select, RW = 0, Address
1
1
X
reSTART, Device Select, RW = 1
Sequential Read
1
X
ā„ 1 Similar to Current or Random Address Read
Byte Write
Page Write
0
VIL
1 START, Device Select, RW = 0
0
VIL
ā¤16 START, Device Select, RW = 0
1. X = VIH or VIL.
Figure 6. Setting the Write Protection Register (WC = 0)
BUS ACTIVITY
MASTER
SDA LINE
CONTROL
BYTE
WORD
ADDRESS
DATA
BUS ACTIVITY
ACK
ACK
ACK
VALUE
VALUE
(DON'T CARE) (DON'T CARE)
AI01935B
12/31
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