M34C02-LDW1G View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M34C02-LDW1G' PDF : 31 Pages View PDF
Initial delivery state
5
Initial delivery state
M34C02-W, M34C02-L, M34C02-R
The device is delivered with all bits in the memory array set to 1 (each Byte contains FFh).
Figure 11. Serial presence detect block diagram
DIMM Position 7
E2 E1 E0 SCL SDA
DIMM Position 6
VCC
E2 E1 E0 SCL SDA
R = 4.7kΩ
DIMM Position 5
VCC
VSS
E2 E1 E0 SCL SDA
DIMM Position 4
VCC VSS VCC
E2 E1 E0 SCL SDA
DIMM Position 3
VCC
VSS
E2 E1 E0 SCL SDA
DIMM Position 2
VSS
VCC
E2 E1 E0 SCL SDA
DIMM Position 1
VSS VCC VSS
E2 E1 E0 SCL SDA
DIMM Position 0
VSS
VCC
E2 E1 E0 SCL SDA
AI01937
VSS
SCL line
SDA line
From the motherboard
I2C master controller
1. E0, E1 and E2 are wired at each DIMM socket in a binary sequence for a maximum of 8 devices.
2. Common clock and common data are shared across all the devices.
3. Pull-up resistors are required on all SDA and SCL bus lines (typically 4.7 kΩ) because these lines are open
drain when used as outputs.
20/31
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