M34C02-LDW1G View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M34C02-LDW1G' PDF : 31 Pages View PDF
Device operation
M34C02-W, M34C02-L, M34C02-R
3.7.3
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Table 14 and Table 16, but the typical time is shorter. To make use of this, a polling
sequence can be used by the bus master.
The sequence, as shown in Figure 9, is:
● Initial condition: a Write cycle is in progress.
● Step 1: the bus master issues a Start condition followed by a Device Select Code (the
first byte of the new instruction).
● Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 9. Write cycle polling flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
First byte of instruction
with RW = 0 already
decoded by the device
NO ACK
Returned
YES
Next
NO
Operation is
Addressing the
Memory
ReSTART
YES
Send Address
and Receive ACK
STOP
NO
START
YES
Condition
DATA for the
WRITE Operation
Continue the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
Random READ Operation
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