M36W416TG, M36W416BG
Figure 22. SRAM Write AC Waveforms, WS Controlled with GS Low
A0-A17
E1S
tAVAV
VALID
tAVWH
tE1LWH
tE2HWH
tWHAX
E2S
UBS, LBS
WS
DQ0-DQ15
tAVWL
tWLQZ
tBLWH
tWLWH
tDVWH
tWHQX
tWHDZ
INPUT VALID
Note: 1. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
Figure 23. SRAM Write Cycle Waveform, UBS and LBS Controlled, GS Low
A0-A17
E1S
tAVAV
VALID
tAVBH
tE1LBH
tE2HBH
AI07946
E2S
UBS, LBS
WS
DQ0-DQ15
tAVBL
tBLBH
tBHAX
tWLBH
tDVBH
tBHDZ
INPUT VALID
Note: 1. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
AI07947
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