M41T81S View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M41T81S' PDF : 29 Pages View PDF
Clock operation
M41T81S
different address. It should also be noted that if the last address written is the “Alarm
Seconds,” the address pointer will increment to the Flag address, causing this situation to
occur.
The IRQ/FT/OUT/SQW output is cleared by a READ to the Flags Register as shown in
Figure 13. A subsequent READ of the Flags Register is necessary to see that the value of
the Alarm Flag has been reset to '0.'
The IRQ/FT/OUT/SQW pin can also be activated in the battery back-up mode. The
IRQ/FT/OUT/SQW will go low if an alarm occurs and both ABE (Alarm in Battery Back-up
Mode Enable) and AFE are set. Figure 14 illustrates the back-up mode alarm timing.
Figure 13. Alarm interrupt reset waveform
0Eh
0Fh
10h
ACTIVE FLAG
IRQ/FT/OUT/SQW
HIGH-Z
AI04617
Figure 14. Back-up mode alarm waveform
VCC
VPFD
VSO
ABE and AFE Bits
AF Bit in Flags
Register
IRQ/FT/OUT/SQW
HIGH-Z
trec
AI09164b
Table 3.
RPT5
1
1
1
1
1
0
Alarm repeat modes
RPT4
RPT3
RPT2
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
RPT1
1
0
0
0
0
0
Alarm Setting
Once per Second
Once per Minute
Once per Hour
Once per Day
Once per Month
Once per Year
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the Watchdog
Register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order
18/31
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