M7010R View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M7010R' PDF : 67 Pages View PDF
M7010R
LEARN is a pipelined operation and last for two
CLK cycles where TLSZ = 00, as shown in Figure
35, page 49, and TLSZ = 01, as shown in Figure
36, page 50 and Figure 37, page 51. Figure 36 and
Figure 37 assume that the device performing the
LEARN operation is not the last device in the table
and has its LRAM Bit set to '0.'
Note: The OE_L for the device with the LRAM Bit
set goes high for two cycles for each LEARN (one
during the SRAM WRITE cycle, and one during
the cycle before it). The latency of the SRAM
WRITE cycle from the second cycle of the instruc-
tion is shown in Table 34, page 51.
Figure 35. LEARN Command Timing Diagram (TLSZ = 00)
CLK 2X
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10
1
3
5
7
9
PHS_L
CMDV
CMD[1:0]
CMD[8:2]
Learn1 X Learn2 X
Comp1
Comp2
AB X
X
DQ
SADR[21:0]
X
X
1A 1B
X
X
ALE_L, CE_L
1
WE_L
1
OE_L
1
0
SSV
0
SSF
0
TLSZ = 00, LRAM = 1, LDEV = 1
A1
A2
0
1
01
0
1
01
0
AI04289
49/67
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