M7010R
Figure 36. LEARN Timing Diagram (TLSZ = 1, except on Last Device)
CLK 2X
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10
1
3
5
7
9
PHS_L
CMDV
CMD[1:0]
CMD[8:2]
Learn1 X Learn2 X
Comp1
Comp2
AB X
X
DQ
z
SADR[21:0]
z
z
ALE_L, CE_L
z
WE_L
OE_L
z
SSV
z
SSF
z
X
X
1A 1B
z
X
X
z = tri-state condition
TLSZ = 00, LRAM = 0, LDEV = 0
z
A1
z
A2
0
0
0
0
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