M7020R-083ZA1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M7020R-083ZA1' PDF : 150 Pages View PDF
Figure 18. Burst WRITE of the Data and Mask Arrays (BLEN = 4)
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6
CLK 2X
M7020R
PHS_L
CMDV
CMD[1:0]
CMD[8:2]
DQ
EOT
Write
AB
Address
Data0 Data1 Data2 Data3
X
AI04285
Table 22. (Single) WRITE Address Format for Data and Mask Arrays or SRAM
DQ
DQ
DQ
DQ
DQ
DQ
[67:30]
[29]
[28:26]
[25:21]
[20:19]
[18:15]
DQ
[14:0]
Successful
SEARCH
Reserved
0: Direct
1: Indirect
Register
Index
(Applicable
ID
if DQ[29] is
indirect)
00: Data
Array
Reserved
If DQ[29] is ’0,’ this field carries the
address of the data array location.
If DQ[29] is ’1,’ the successful
search register specified by
DQ[28:26] supplies the address of
the data array location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0]
| DQ[0]}(1)
Successful
SEARCH
Reserved
0: Direct
1: Indirect
Register
Index
(Applicable
ID
if DQ[29] is
indirect)
01: Mask
Array
Reserved
If DQ[29] is ’0,’ this field carries
address of the mask array location.
If DQ[29] is ’1,’ the successful
search register specified by
DQ[28:26] supplies the address of
the mask array location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0]
| DQ[0]}(1)
Successful
SEARCH
Reserved
0: Direct
1: Indirect
Register
Index
(Applicable
ID
if DQ[29] is
indirect)
10:
External
SRAM
Reserved
If DQ[29] is ’0,’ this field carries
address of the data SRAM location.
If DQ[29] is ’1,’ the successful
search register specified by
DQ[28:26] supplies the address of
the SRAM location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0]
| DQ[0]}(1)
Note: 1. “|” stands for Logical OR operation. “{ }” stands for concatenation operator.
35/150
Share Link: 
