M95320-DRE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M95320-DRE' PDF : 41 Pages View PDF
M95320-DRE
Instructions
4.8
Write Identification Page (WRID)
The Write Identification Page instruction is used to write the Identification Page (additional
page of 32 bytes which can also be permanently locked in Read-only mode).
The Chip Select signal (S) is first driven low, and then the bits of the instruction byte,
address bytes, and at least one data byte are shifted in (MSB first) on Serial Data input (D).
Address bit A10 must be 0 and the other upper address bits are Don't Care (it might be
easier to define these bits as 0, as shown in Table 7). The lower address bits [A4:A0] define
the byte address inside the identification page.
The self-timed Write cycle starts from the rising edge of Chip Select (S), and continues for a
period tW (as specified in Table 13).
Figure 13. Write Identification Page sequence
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The first three bytes of the Identification page offer the Device Identification code (Please
refer to Section 3.5: Identification page for more information). Using the WRID command on
these first three bytes overwrites the Device Identification code.
The instruction is discarded, and is not executed, under the following conditions:
• If a Write cycle is already in progress
• If the Block Protect bits (BP1,BP0) = (1,1)
• If one of the conditions defined in Section 3.4.1: Protocol control is not satisfied.
4.9
Read Lock Status (RDLS)
The Read Lock Status instruction is used to read the lock status.
To send this instruction to the device, Chip Select (S) first has to be driven low. The bits of
the instruction byte and address bytes are then shifted in (MSB first) on Serial Data input
(D). Address bit A10 must be 1; all other address bits are Don't Care (it might be easier to
define these bits as 0, as shown in Table 7). The Lock bit is the LSB (Least Significant Bit) of
the byte read on Serial Data output (Q). It is at ‘1’ when the lock is active and at ‘0’ when the
lock is not active. If Chip Select (S) continues to be driven low, the same data byte is shifted
out.
The read cycle is terminated by driving Chip Select (S) high. The instruction sequence is
shown in Figure 14.
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