M95320-DRE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M95320-DRE' PDF : 41 Pages View PDF
M95320-DRE
Application design recommendations
5.1.3
Power-down
At power down, the power-on-reset (POR) circuit resets and locks the device as soon as the
VCC reached the internal threshold voltage
During power-down (continuous decrease in the VCC supply voltage below the minimum
VCC operating voltage defined in Table 12), the device must be:
• deselected (Chip Select (S) should be allowed to follow the voltage applied on VCC),
• in Standby power mode (there should not be any internal Write cycle in progress).
5.2
Implementing devices on SPI bus
Figure 16 shows an example of three devices, connected to the SPI bus master. Only one
device is selected at a time, so that only the selected device drives the Serial Data output
(Q) line. All the other devices outputs are then in high impedance.
Figure 16. Bus master and memory devices on the SPI bus
6##
30) INTERFACE WITH
#0/, #0(!
OR
3$/
3$)
3#+
30) BUS MASTER
2
#3 #3 #3
# 1 $ 6##
#1$
6##
30) MEMORY
DEVICE
2
3 7 (/,$
30) MEMORY
DEVICE
2
3 7 (/,$
# 1 $ 6##
30) MEMORY
DEVICE
3 7 (/,$
633
-36
1. The Write Protect (W) and Hold (HOLD) signals must be driven high or low as appropriate.
A pull-up resistor connected on each /S input (represented in Figure 16) ensures that each
device is not selected if the bus master leaves the /S line in the high impedance state.
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