MC2502 View Datasheet(PDF) - PMD
Part Name
Description
MFG CO.
'MC2502' PDF : 51 Pages View PDF
8
7
6
5
4
3
2
1
R?
VCC
VCC
22K
DS[0..15]
A[0..15]
U1
U?
DS[0..15]
D
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DS11
DS12
DS13
DS14
DS15
9
10
11
12
15
16
17
18
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
19
22
23
24
25
26
27
28
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
53 I/OINTRP
63 POSLIM1
65
54
49
POSLIM2
POSLIM3
POSLIM4
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
110
111
112
114
115
116
117
118
119
122
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
N/C
~RAMSLCT
~PERIPHSLCT
R/~W
~STROBE
~WRITEENBL
123
124
125
126
127
128
131
129
130
4
6
1
W/~R 132
~HOSTINTRPT 98
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
IS-
STRB-
W/R
A11
NOTE:FS INPUTS ARE +- 10V
U2
2
1
2 U2
3
1
4
5
OR4
POS1
POS2
POS3
POS4
CVT-
DACRD-
1 VIN1
2 VIN2
27 VIN3
28 VIN4
5 CONVST
6 RD
7 CS
24 REFIN
25 REFOUT
8 CLK
DB11 10
DB10 11
DB9 12
DB8 13
DB7 15
DB6 16
DB5 17
DB4 18
DB3 19
DB2 20
DB1 21
DB0 22
DS11
DS10
DS9
DS8
DS7
DS6
DS5
DS4
DS3
DS2
DS1
DS0
DS11
DACRD-
U2
2
4
6
8
11
13
1A1
1A2
1A3
1A4
2A1
2A2
15
17
2A3
2A4
1
19
1G
2G
74LS244
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
18
16
14
12
9
7
DS15
DS14
DS13
DS12
2Y3
2Y4
5
3
NOTE:SIGN EXTENTION FOR 2'S COMPLEMENT
D
64
66
NEGLIM1
NEGLIM2
AXISOUT1 94
55 NEGLIM3
AXISOUT2 95
C
51 NEGLIM4
AXISOUT3
AXISOUT4
96
97
NOT
INT 4
AD7874
C
73
90
91
HALL1A
HALL1B
HALL1C
SRLRCV
SRLXMT
43
44
-5VA
GND
101
102
105
107
HALL2A
HALL2B
HALL2C
HALL3A
SYNCH
SRLENABLE
45
99
VCC
U2
3A
QA 14
VCC
U2
3A
QA 14
AGND
108
109
68
69
70
HALL3B
HALL3C
HALL4A
HALL4B
HALL4C
72
100
106
67
AXISIN1
AXISIN2
AXISIN3
AXISIN4
ANALOG1
ANALOG2
ANALOG3
ANALOG4
ANALOG5
ANALOG6
74
89
75
88
76
83
ANALOG7
ANALOG8
77
82
ANALOGVCC
ANALOGREFHIGH
84
85
CLK
DACRD-
GND
ENCNT-
4
5
6
2
9
B
QB
C
QC
D
QD
RCO
CLK
LOAD
13
12
11
15
1
10
7
U/D
ENT
ENP
74ALS169
CLK
DACRD-
GND
4
5
6
2
9
B
QB
C
QC
D
QD
RCO
CLK
LOAD
13
12
11
15
1
10
7
U/D
ENT
ENP
74ALS169
CVT-
U2
2
1
NOT
CLK
U2
DFF2
2D
3 CLK
Q 1 ENCNT-
30
31
N/C
N/C
ANALOGREFLOW
ANALOGGND
86
87
34
33
N/C
N/C
B
32 N/C
38
39
N/C
N/C
N/C
N/C
N/C
N/C
78
79
80
81
DACRD- WILL LOAD THE COUNTER TO 255.
12.8 USEC. AFTER THE LAST DACRD-
THE COUNTER WILL REACH 0 AND START THE
NEXT CONVERSION. ALL 4 CHANNELS WILL
BE CONVERTED IN 35 USEC. READY FOR
DACRD-
B
RS-
41 ~RESET
THE NEXT SET OF READS 50 USEC LATER.
CLK
58 I/OCK
CP2N40
NOTE:THE LOGIC LABELED U2 MAY
BE IMPLEMENTEDIN A PLD.
GND
A
A
PERFORMANCE MOTION DEVICES
55 OLD BEFORD RD
LINCOLN, MA 01773
Title
12 BIT A/D IN (GEN2DC1)
Size Document Number
Rev
B
B
Date: Thursday, April 11, 2002
Sheet
1
of 0
8
7
6
5
4
3
2
1
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