MC2502 View Datasheet(PDF) - PMD
Part Name
Description
MFG CO.
'MC2502' PDF : 51 Pages View PDF
8
R?
22K
DS[0..15]
D
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DS11
DS12
DS13
DS14
DS15
9
10
11
12
15
16
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
17
18
19
22
23
24
25
26
27
28
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
53 I/OINTRP
63
65
POSLIM1
POSLIM2
54
49
POSLIM3
POSLIM4
64 NEGLIM1
C
66
55
NEGLIM2
NEGLIM3
51 NEGLIM4
73
90
91
101
102
105
107
108
109
68
69
HALL1A
HALL1B
HALL1C
HALL2A
HALL2B
HALL2C
HALL3A
HALL3B
HALL3C
HALL4A
HALL4B
70 HALL4C
72
100
106
67
AXISIN1
AXISIN2
AXISIN3
AXISIN4
30
31
N/C
N/C
B
34 N/C
33
32
N/C
N/C
38
39
N/C
N/C
RS-
41 ~RESET
CLK
58 I/OCK
VCC
U2
A
CLK
DACRD-
GND
ENCNT-
3
4
5
6
2
9
1
10
7
A
QA
B
QB
C
QC
D
QD
RCO
CLK
LOAD
U/D
ENT
ENP
14
13
12
11
15
74ALS169
8
7
6
5
4
3
2
1
DS[0..15]
+5A
VCC
U2
VCC
3 D0
Q0 2
A[0..15]
U1
4 D1
Q1 5
U3
7
8
D2
D3
Q2
Q3
6
9
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
110
111
112
114
115
116
117
118
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
N/C
~RAMSLCT
~PERIPHSLCT
R/~W
119
122
123
124
125
126
127
128
131
129
130
4
~STROBE
~WRITEENBL
W/~R
6
1
132
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
IS-
STRB-
W/R
A11n
2 U2
3
4
5
OR4
A0
A1
1 DACRD-
NOTE:FS INPUTS ARE +- 10V
R1
AIN1
200
U2A
2
3
A
B
1G
139
Y0
Y1
Y2
4
5
6
Y3 7
RD1-
RD2-
RD3-
RD4-
R2
33.2
CVT-
GND
1 VIN
3 REF
4 CAP
25 CS
24 R/C
23 BYTE
C1
2.2UF
C1
2.2UF
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BUSY
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
26
AD976
GND
RD1-
13
14
17
18
D4
D5
D6
D7
1
11
OC
CLK
374
U2
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
1
11
OC
CLK
374
Q4
Q5
Q6
Q7
12
15
16
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
D
~HOSTINTRPT 98
U2
AGND
AXISOUT1
AXISOUT2
AXISOUT3
AXISOUT4
94
95
96
97
SRLRCV
SRLXMT
43
44
SYNCH
SRLENABLE
45
99
ANALOG1
ANALOG2
ANALOG3
ANALOG4
74
89
75
88
ANALOG5
ANALOG6
ANALOG7
ANALOG8
76
83
77
82
ANALOGVCC
ANALOGREFHIGH
ANALOGREFLOW
ANALOGGND
84
85
86
87
N/C
N/C
78
79
N/C
N/C
80
81
A11
2
1 A11n
NOT
NOTE:THE LOGIC LABELED U2 MAY
BE IMPLEMENTEDIN A PLD.
C
R3
AIN2
200
R4
33.2
CVT-
GND
+5A
1 VIN
3 REF
4 CAP
25 CS
24 R/C
23 BYTE
VCC
U4
D15
D14
D13
D12
D11
D10
6
7
8
9
10
11
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
12
13
15
16
17
18
19
20
21
22
U2
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
1
11
OC
CLK
374
U2
3
4
D0
D1
Q0
Q1
2
5
7 D2
Q2 6
8
13
D3
D4
Q3
Q4
9
12
14
17
D5
D6
Q5
Q6
15
16
18 D7
Q7 19
B
C1
2.2UF
C1
2.2UF
BUSY 26
AD976
RD2-
1 OC
11 CLK
374
GND
CP2N40
AGND
GND
VCC
CLK
DACRD-
GND
U2
3
4
5
6
2
9
1
10
7
A
QA
B
QB
C
QC
D
QD
RCO
CLK
LOAD
U/D
ENT
ENP
14
13
12
11
15
74ALS169
VCC
GND
CLK
DACRD-
GND
U2
3
4
5
6
2
9
1
10
7
A
QA
B
QB
C
QC
D
QD
RCO
CLK
LOAD
U/D
ENT
ENP
14
13
12
11
15
74ALS169
CVT-
7
6
U2
2
1
NOT
CLK
5
U2
DFF2
2D
3 CLK
Q 1 ENCNT-
DACRD-
DACRD- WILL LOAD THE COUNTER TO 700.
38.4 USEC. AFTER THE LAST DACRD-
THE COUNTER WILL REACH 0 AND START THE
NEXT CONVERSION. ALL 4 CHANNELS WILL
BE CONVERTED IN 10 USEC. READY FOR
THE NEXT SET OF READS AFTER 50 USEC.
4
NOTE:AXIS 1 AND 2 ARE SHOWN EXPLICITLY.
AXIS 3 AND 4 MAY BE IMPLEMENTED IN AN
IDENTICAL FASHION.
SEE ANALOG DEVICES SPECIFICATIONS FOR
ADITIONAL INFORMATION AND POWER BYPASSING.
PERFORMANCE MOTION DEVICES
55 OLD BEDFORD RD
LINCOLN, MA 01773
Title
16 BIT A/D INPUT (GEN2DL1)
Size Document Number
B
Date: Thursday, April 11, 2002
3
2
A
Sheet
Rev
B
1
of 1
1
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