MC9S08QA2 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MC9S08QA2' PDF : 32 Pages View PDF
Electrical Characteristics
3.8.1 Control Timing
Table 9. Control Timing
Parameter
Symbol
Min
Typical1
Max
Unit
Bus frequency (tcyc = 1/fBus)
Real-time interrupt internal oscillator period (see Table 9)
External reset pulse width2
IRQ pulse width
Asynchronous path2
Synchronous path3
KBIPx pulse width
Asynchronous path2
Synchronous path3
Port rise and fall time (load = 50 pF)4
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
fBus
tRTI
textrst
tILIH
tILIH, tIHIL
tRise, tFall
0
700
100
100
1.5 tcyc
100
1.5 tcyc
—
—
—
1000
—
—
—
3
30
10
1300
—
—
MHz
μs
ns
ns
—
ns
—
ns
—
BKGD/MS setup time after issuing background debug force
tMSSU
500
—
reset to enter user or BDM modes
—
ns
BKGD/MS hold time after issuing background debug force
reset to enter user or BDM modes5
tMSH
100
—
—
μs
1 Data in Typical column was characterized at 3.0 V, 25°C.
2 This is the shortest pulse that is guaranteed to be recognized.
3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.
5 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD.
1600
1400
1200
1000
Period (μs)
800
600
400
200
0
–40
–40
0
20
40
60
80
100
Temperature (°C)
Figure 9. Typical RTI Clock Period vs. Temperature
= +3 σ
= Mean
= –3 σ
MC9S08QA4 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
13
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